Session 17 - Clocking circuits. - Dennis Michael Fischette; Kimo Tam (CICC, 2008)

An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI. - Dennis Michael Fischette; Richard Joseph DeSantis; John H. Lee (CICC, 2009)

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. - Dennis Michael Fischette; Alvin Leng Sun Loke; Michael M. Oshima; Bruce Andrew Doyle; Roland Bakalski; Richard Joseph DeSantis; Anand Thiruvengadam; Charles Lin Wang; Gerry R. Talbot; Emerson S. Fang (ISSCC, 2010)

An Embedded All-Digital Circuit to Measure PLL Response. - Dennis Michael Fischette; Alvin Leng Sun Loke; Richard Joseph DeSantis; Gerry R. Talbot (IEEE J. Solid State Circuits, 2010)

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. - Bruce Andrew Doyle; Alvin Leng Sun Loke; Sanjeev K. Maheshwari; Charles Lin Wang; Dennis Michael Fischette; Jeffrey G. Cooper; Sanjeev K. Aggarwal; Tin Tin Wee; Chad O. Lackey; Harishkumar S. Kedarnath; Michael M. Oshima; Gerry R. Talbot; et al. (A-SSCC, 2011)

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors. - Alvin Leng Sun Loke; Bruce Andrew Doyle; Sanjeev K. Maheshwari; Dennis Michael Fischette; Charles Lin Wang; Tin Tin Wee; Emerson S. Fang (IEEE J. Solid State Circuits, 2012)

Wireline transmitter and receiver design techniques. - Dennis Michael Fischette; Jaeha Kim (CICC, 2013)

Wireline clocking and equalization. - William Walker; Dennis Michael Fischette (CICC, 2014)