Parametrized Exceptions. - Dennis Walter; Lutz Schröder; Till Mossakowski (CALCO, 2005)

Zertifizierung einer Sicherungskomponente mittels durchgängig formaler Modellierung. - Udo Frese; Daniel Hausmann 001; Christoph Lüth; Holger Täubig; Dennis Walter (Software Engineering (Workshops), 2008)

The Importance of Being Formal. - Udo Frese; Daniel Hausmann 001; Christoph Lüth; Holger Täubig; Dennis Walter (SafeCert@ETAPS, 2008)

Integration of a security type system into a program logic. - Reiner Hähnle; Jing Pan; Philipp Rümmer; Dennis Walter (Theor. Comput. Sci., 2008)

Certifiable Specification and Verification of C Programs. - Christoph Lüth; Dennis Walter (FM, 2009)

Efficient compensation of delay variations in high-speed network-on-chip data links. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; René Schüffny (SoC, 2010)

Experiences in Applying Formal Verification in Robotics. - Dennis Walter; Holger Täubig; Christoph Lüth (SAFECOMP, 2010)

A formal verification environment for use in the certification of safety-related C-programs. - Dennis Walter (2010)

Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (SoC, 2011)

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. - Dennis Walter; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stephan Henker; Stefan Hänzsche; René Schüffny; Markus Winter 002; Gerhard P. Fettweis (ISSCC, 2012)

Guaranteeing functional safety: design for provability and computer-aided verification. - Holger Täubig; Udo Frese; Christoph Hertzberg; Christoph Lüth; Stefan Mohr; Elena Vorobev; Dennis Walter (Auton. Robots, 2012)

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (Int. J. Embed. Real Time Commun. Syst., 2012)

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; Stefan Schiefer; René Schüffny (ECCTD, 2013)

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. - Sebastian Höppner; Stefan Hänzsche; Georg Ellguth; Dennis Walter; Holger Eisenreich; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. - Sebastian Höppner; Holger Eisenreich; Stephan Henker; Dennis Walter; Georg Ellguth; René Schüffny (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An energy efficient multi-bit TSV transmitter using capacitive coupling. - Johannes Gorner; Sebastian Höppner; Dennis Walter; Michael Haas; Dirk Plettemeier; René Schüffny (ICECS, 2014)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

A deep-submicron CMOS flow for general-purpose timing-detection insertion. - Andreas Dixius; Dennis Walter; Sebastian Höppner; Holger Eisenreich; René Schüffny (MIXDES, 2015)

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. - Sebastian Höppner; Dennis Walter; Thomas Hocker; Stephan Henker; Stefan Hänzsche; Daniel Sausner; Georg Ellguth; Jens-Uwe Schluessler; Holger Eisenreich; René Schüffny (IEEE J. Solid State Circuits, 2015)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Exploiting transistor-level reconfiguration to optimize combinational circuits. - Michael Raitza; Akash Kumar 001; Marcus Völp; Dennis Walter; Jens Trommer; Thomas Mikolajick; Walter M. Weber (DATE, 2017)

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology. - Heiner Bauer; Sebastian Höppner; Johannes Partzsch; Dennis Walter; Christian Mayr 001; Florian Schraut; Holger Eisenreich (NORCAS, 2017)

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. - Shubham Rai; Ansh Rupani; Dennis Walter; Michael Raitza; Andre Heinzig; Tim Baldauf; Jens Trommer; Christian Mayr 001; Walter M. Weber; Akash Kumar 001 (DATE, 2018)

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. - Sebastian Höppner; Jörg Schreiter; Robert Niebsch; Stephan Scherzer; Ulrich Hensel; Jörg Winkler; Mario Orgis; Holger Eisenreich; Dennis Walter; Uwe Steeb; André Scharfe; Clifford Dmello; et al. (ESSDERC, 2019)

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. - Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Heiner Bauer; Farkas Csaszar; Robert Niebsch; Jörg Schreiter; Holger Eisenreich; Sebastian Höppner (COOL CHIPS, 2020)

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. - Sebastian Höppner; Holger Eisenreich; Dennis Walter; André Scharfe; Alexander Oefelein; Florian Schraut; Jörg Schreiter; Thorsten Riedel; Heiner Bauer; Robert Niebsch; Stephan Scherzer; Thomas Hocker; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. - Sebastian Höppner; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Marco Stolba; Florian Kelber; Bernhard Vogginger; Felix Neumärker; Georg Ellguth; Stephan Hartmann 002; Stefan Schiefer; et al. (CoRR, 2021)

Hardware Implementation of an OPC UA Server for Industrial Field Devices. - Heiner Bauer; Sebastian Höppner; Chris Paul Iatrou; Zohra Charania; Stephan Hartmann 002; Saif-Ur Rehman; Andreas Dixius; Georg Ellguth; Dennis Walter; Johannes Uhlig; Felix Neumärker; Marc Berthel; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2021)

ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data. - Matthias Jobst; Johannes Partzsch; Chen Liu 031; Liyuan Guo; Dennis Walter; Saif-Ur Rehman; Stefan Scholze; Sebastian Höppner; Christian Mayr 001 (AICAS, 2022)

A 16-Channel Fully Configurable Neural SoC With 1.52 $ mu$W/Ch Signal Acquisition, 2.79 $ mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. - Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Richard George 001; Florian Kelber; Heiner Bauer; Stefan Scholze; Stefan Hänzsche; Marco Stolba; Andreas Dixius; Georg Ellguth; Dennis Walter; Sebastian Höppner; et al. (IEEE Trans. Biomed. Circuits Syst., 2022)

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. - Hector A. Gonzalez; Bernhard Vogginger; Chen Liu 031; Marco Stolba; Florian Kelber; Heiner Bauer; Stefan Hänzsche; Stefan Scholze; Marc Berthel; Tim Rosmeisl; Liyuan Guo; Dennis Walter; et al. (CICC, 2023)

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. - Heiner Bauer; Marco Stolba; Stefan Scholze; Dennis Walter; Christian Mayr 001; Alexander Oefelein; Sebastian Höppner; André Scharfe; Florian Schraut; Holger Eisenreich (ISOCC, 2023)

NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications. - Amirhossein Rostami; Seyed Mohammad Ali Zeinolabedin; Liyuan Guo; Florian Kelber; Heiner Bauer; Andreas Dixius; Stefan Scholze; Marc Berthel; Dennis Walter; Johannes Uhlig; Bernhard Vogginger; Christian Mayr 001 (IEEE Open J. Circuits Syst., 2025)