A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller. - Deog-Kyoon Jeong; David A. Wood 001; Garth A. Gibson; Susan J. Eggers; David A. Hodges; Randy H. Katz; David A. Patterson 001 (IEEE J. Solid State Circuits, 1989)

An on-chip smart memory for a data-flow CPU. - Gregory A. Uvieghara; Yoshinobu Nakagome; Deog-Kyoon Jeong; David A. Hodges (IEEE J. Solid State Circuits, 1990)

An experimental single-chip data flow CPU. - Gregory A. Uvieghara; Wen-mei W. Hwu; Yoshinobu Nakagome; Deog-Kyoon Jeong; David D. Lee; David A. Hodges; Yale N. Patt (IEEE J. Solid State Circuits, 1992)

Threaded prefetching: An adaptive instruction prefetch mechanism. - Seong Baeg Kim; Myung Soon Park; Sun-Ho Park; Sang Lyul Min; Heonshik Shin; Chong-Sang Kim; Deog-Kyoon Jeong (Microprocess. Microprogramming, 1993)

V-P cache: a storage efficient virtual cache organization. - Sang Lyul Min; Jesung Kim; Chong-Sang Kim; Heonshik Shin; Deog-Kyoon Jeong (Microprocess. Microsystems, 1993)

Class-AB large-swing CMOS buffer amplifier with controlled bias current. - Joongsik Kih; Byungsoo Chang; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 1993)

Hotpads - macro-dells for gigabit I/O. - Deog-Kyoon Jeong; David D. Lee; J. Duane Northcutt; Andreas von Bechtolsheim; David R. Ditzel; Amnon Fisher (Hot Interconnects, 1994)

A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. - Daejong Kim; Jaejin Park; Sungjoon Kim; Deog-Kyoon Jeong; Wonchan Kim (ISCAS, 1994)

U-Cache: A Cost-Effective Solution to the Synonym Problem. - Jesung Kim; Sang Lyul Min; Sanghoon Jeon 002; ByoungChul Ahn; Deog-Kyoon Jeong; Chong-Sang Kim (HPCA, 1995)

A CMOS serial link for fully duplexed data communication. - Kyeongho Lee; Sungjoon Kim; Gijung Ahn; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 1995)

A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. - Daejeong Kim; Jaejin Park; Sungjoon Kim; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 1995)

An efficient charge recovery logic circuit. - Yong Moon; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 1996)

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. - Sungjoon Kim; Kyeongho Lee; Yongsam Moon; Deog-Kyoon Jeong; Yunho Choi; Hyung Kyu Lim (IEEE J. Solid State Circuits, 1997)

Design and Implementation of OTCA MAC Protocol for High-Speed Point-to-Point Ring Network. - Yeshik Shin; Jin-su Ahn; Hyung-Rok Lee; Deog-Kyoon Jeong (LCN, 1998)

1.04 GBd low EMI digital video interface system using small swing serial link technique. - Kyeongho Lee; Yeshik Shin; Sungjoon Kim; Deog-Kyoon Jeong; Gyudong Kim; Bruce Kim; Victor Da Costa (IEEE J. Solid State Circuits, 1998)

A 32×32-b adiabatic register file with supply clock generator. - Yong Moon; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 1998)

A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. - Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim (CICC, 1999)

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission. - Gijung Ahn; Deog-Kyoon Jeong; Gyudong Kim (IEEE J. Solid State Circuits, 2000)

A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers. - Jong-Seok Kim; Deog-Kyoon Jeong; Gyudong Kim (IEEE J. Solid State Circuits, 2000)

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. - Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim (IEEE J. Solid State Circuits, 2000)

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. - Kyeongho Lee; Joonbae Park; Jeong-Woo Lee; Seung-Wook Lee; Hyung Ki Huh; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2001)

A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. - Yongsam Moon; Deog-Kyoon Jeong; Gijung Ahn (IEEE J. Solid State Circuits, 2001)

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. - Yido Koo; Hyungki Huh; Yongsik Cho; Jeongwoo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2002)

A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. - Sang-Hyun Lee; Moon-Sang Hwang; Youngdon Choi; Sungjoon Kim; Yongsam Moon; Bong-Joon Lee; Deog-Kyoon Jeong; Wonchan Kim; Young-June Park; Gijung Ahn (IEEE J. Solid State Circuits, 2002)

A dual-mode direct-conversion CMOS transceiver for Bluetooth and 802.11b. - Yeon-Jae Jung; Hoesam Jeong; Eunseok Song; Jungho Lee; Seung-Wook Lee; Donghyeon Seo; Inho Song; Sanghun Jung; Joonbae Park; Deog-Kyoon Jeong; Wonchan Kim (ESSCIRC, 2003)

Multi-gigabit-rate clock and data recovery based on blind oversampling. - Jaeha Kim; Deog-Kyoon Jeong (IEEE Commun. Mag., 2003)

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization. - Bong-Joon Lee; Moon-Sang Hwang; Sang-Hyun Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2003)

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. - Kang-Yoon Lee; Seung-Wook Lee; Yido Koo; Hyoung-Ki Huh; Hee-Young Nam; Jeong-Woo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2003)

Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery. - Youngdon Choi; Deog-Kyoon Jeong; Wontae Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method. - Jong-Sang Choi; Moon-Sang Hwang; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2004)

A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b. - Yeon-Jae Jung; Hoesam Jeong; Eunseok Song; Jungho Lee; Seung-Wook Lee; Donghyeon Seo; Inho Song; Sanghun Jung; Joonbae Park; Deog-Kyoon Jeong; Soo-Ik Chae; W. Kim (IEEE J. Solid State Circuits, 2004)

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. - Yongsam Moon; Young-Soo Park; Namhoon Kim; Gijung Ahn; Hyun J. Shin; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2004)

A single-chip storage LSI for home networks. - Hankyu Lim; Deog-Kyoon Jeong; KyungTae Kim; JunMo Park; Han-Gyoo Kim (IEEE Commun. Mag., 2005)

Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. - Hyungki Huh; Yido Koo; Kang-Yoon Lee; Yeonkyeong Ok; Sungho Lee; Daehyun Kwon; Jeongwoo Lee; Joonbae Park; Kyeongho Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2005)

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique. - Hyung-Rok Lee; Moon-Sang Hwang; Bong-Joon Lee; Young-Deok Kim; Dohwan Oh; Jaeha Kim; Sang-Hyun Lee; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2005)

A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification. - Young-Deok Kim; Hyun-Seok Ahn; Joon-Young Park; Suhwan Kim 001; Deog-Kyoon Jeong (ISSCC, 2006)

A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm. - Hyung-Rok Lee; Ook Kim; Keewook Jung; John Shin; Deog-Kyoon Jeong (ISSCC, 2006)

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS. - Jaeha Kim; Jeong-Kyoum Kim; Bong-Joon Lee; Namhoon Kim; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2006)

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters. - Hwi-Cheol Kim; Deog-Kyoon Jeong; Wonchan Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. - Do-Hwan Oh; Deok-Soo Kim; Suhwan Kim 001; Deog-Kyoon Jeong; Wonchan Kim (ISSCC, 2007)

Enhanced token bucket policer using reduced fair queuing for Ethernet access networks. - Chul-Ki Lee; Jae-Hwa Kwak; Deog-Kyoon Jeong (IET Commun., 2007)

Virtual minimum potential queuing. - Chul Ki Lee; Deog-Kyoon Jeong; Yong Chul Shim (J. High Speed Networks, 2007)

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme. - Won-Jun Choe; Bong-Joon Lee; Jaeha Kim; Deog-Kyoon Jeong; Gyudong Kim (IEEE J. Solid State Circuits, 2007)

A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. - Hoesam Jeong; Byoung-Joo Yoo; Cheol Kyu Han; Sang-Yoon Lee 006; Kang-Yoon Lee; Suhwan Kim 001; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2007)

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. - Yongho Lee; Deog-Kyoon Jeong; Taewhan Kim (ICCAD, 2008)

An ethernet switch architecture for bandwidth provision of broadband access networks. - Jonghoon Lee; Chul-Ki Lee; Jiho Han; Hanku Chi; Taesik Na; Deog-Kyoon Jeong; Jae-Hwa Kwak; Jin-su Ahn; Sangho Yoon (IEEE Commun. Mag., 2008)

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation. - Byoung-Mo Moon; Young-June Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. - Nan Xing; Heesoo Song; Deog-Kyoon Jeong; Suhwan Kim 001 (SoCC, 2009)

Practical considerations in the design and implementation of time synchronization systems using IEEE 1588. - Jiho Han; Deog-Kyoon Jeong (IEEE Commun. Mag., 2009)

A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver. - Jeong-Kyoum Kim; Jaeha Kim; Gyudong Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2009)

A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification. - Young-Deok Kim; Hyun-Seok Ahn; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits. - Jaeha Kim; Jeong-Kyoum Kim; Bong-Joon Lee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer. - Jong-Kwan Woo; Dong-Yong Shin; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Consumer Electron., 2009)

A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment. - Jiho Han; Hankyu Chi; Deog-Kyoon Jeong (ISCAS, 2010)

A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. - Deok-Soo Kim; Heesoo Song; Taeho Kim; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2010)

A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems. - Jiho Han; Deog-Kyoon Jeong (IEEE Trans. Instrum. Meas., 2010)

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit. - Sungchun Jang; Heesoo Song; Seokmin Ye; Deog-Kyoon Jeong (ISSCC, 2011)

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. - Woo-Yeol Shin; Gi-Moon Hong; Hyongmin Lee; Jaeduk Han; Sunkwon Kim; Kyu-Sang Park; Dong-Hyuk Lim; Jung-Hoon Chun; Deog-Kyoon Jeong; Suhwan Kim 001 (ISSCC, 2011)

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. - Sang-Yoon Lee; Hyung-Rok Lee; Young-Ho Kwak; Woo-Seok Choi; Byoung-Joo Yoo; Daeyun Shim; Chulwoo Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)

A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. - Heesoo Song; Deok-Soo Kim; Do-Hwan Oh; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)

A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines. - Yohwan Yoon; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits. - Yongho Lee; Deog-Kyoon Jeong; Taewhan Kim (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A low-noise differential front-end and its controller for capacitive touch screen panels. - Dong-Hyuk Lim; Jun-Eun Park; Deog-Kyoon Jeong (ESSCIRC, 2012)

A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. - Jaeha Kim; Sigang Ryu; Byoung-Joo Yoo; Hanseok Kim; Yunju Choi; Deog-Kyoon Jeong (ISCAS, 2012)

Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. - Woo-Rham Bae; Byoung-Joo Yoo; Deog-Kyoon Jeong (ISOCC, 2012)

A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology. - Taeho Kim; Deog-Kyoon Jeong (ISOCC, 2012)

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS. - Dong-Wook Kim; Hankyu Chi; Yu-Sang Chun; Myung-Heon Chin; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2013)

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. - Wooseok Kim; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (ISSCC, 2013)

A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM. - Daeyong Shim; Hyunsik Jeong; Hyunjoong Lee; Cyuyeol Rhee; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2013)

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (A-SSCC, 2014)

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. - Woo-Rham Bae; Deog-Kyoon Jeong; Byoung-Joo Yoo (DDECS, 2014)

A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth. - Woo-Rham Bae; Deog-Kyoon Jeong (ICEIC, 2014)

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. - Woo-Rham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2014)

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS. - Gyu-Seob Jeong; Hankyu Chi; Kyungock Kim; Deog-Kyoon Jeong (ISCAS, 2014)

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS. - Yoonsoo Kim; Woo-Rham Bae; Deog-Kyoon Jeong (ISCAS, 2014)

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. - Wooseok Kim; Jaejin Park; Hojin Park; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2014)

A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels. - Jun-Eun Park; Dong-Hyuk Lim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2014)

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. - Taeho Kim; Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Jiheon Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS. - Jong-Kwan Woo; Hyunjoong Lee; Hwi-Cheol Kim; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. - Byoung-Joo Yoo; Woo-Rham Bae; Jiho Han; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong (A-SSCC, 2015)

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. - Joo-Hyung Chae; Gi-Moon Hong; Jihwan Park; Mino Kim; Hyeongjun Ko; Woo-Yeol Shin; Hankyu Chi; Deog-Kyoon Jeong; Suhwan Kim 001 (A-SSCC, 2015)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Jinhyung Lee; Han-Gon Ko; Sungchun Jang; Sang-Hyeok Chu; Woo-Rham Bae; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2015)

A low-power pulse position modulation transceiver. - Woo-Rham Bae; Chang-Soo Yoon; Deog-Kyoon Jeong (ISCAS, 2015)

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. - Sungwoo Kim 001; Sungchun Jang; Jun-Eun Park; Yoonsoo Kim; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2015)

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. - Kwanseo Park; Woo-Rham Bae; Haram Ju; Jinhyung Lee; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (ISCAS, 2015)

20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS. - Jun-Eun Park; Yoonsoo Kim; Sungwoo Kim 001; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2015)

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (VLSIC, 2015)

A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances. - Woo-Rham Bae; Deog-Kyoon Jeong (Int. J. Circuit Theory Appl., 2015)

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Sungchun Jang; Sungwoo Kim 001; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2015)

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong (A-SSCC, 2016)

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. - Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. - Haram Ju; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A theoretical analysis of phase shift in pulse injection-locked oscillators. - Jinhyung Lee; Sungwoo Kim 001; Min-Seong Choo; Sung-Yong Cho; Han-Gon Ko; Deog-Kyoon Jeong (ISCAS, 2016)

11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp. - Jun-Eun Park; Jiheon Park; Young-Ha Hwang; Jonghyun Oh; Deog-Kyoon Jeong (ISSCC, 2016)

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. - Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Kwanseo Park; Sung-Yong Cho; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

20-Gb/s 5-VPP and 25-Gb/s 3.8-VPP Area-Efficient Modulator Drivers in 65-nm CMOS. - Yoonsoo Kim; Gyu-Seob Jeong; Jun-Eun Park; Joonbae Park; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Yoonsoo Kim; Hankyu Chi; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications. - Young-Ha Hwang; Jun-Eun Park; Deog-Kyoon Jeong (A-SSCC, 2017)

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. - Kwanseo Park; Woo-Rham Bae; Deog-Kyoon Jeong (CICC, 2017)

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. - Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Jinhyung Lee; Soyeong Shin; Min-Seong Choo; Hankyu Chi; Deog-Kyoon Jeong (ISSCC, 2017)

Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016). - Deog-Kyoon Jeong; Jaeha Kim (IEEE J. Solid State Circuits, 2017)

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. - Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (Sensors, 2017)

A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. - Gyu-Seob Jeong; Wooseok Kim; Jaejin Park; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS. - Jun-Eun Park; Young-Ha Hwang; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. - Kwanseo Park; Jinhyung Lee; Kwangho Lee; Min-Seong Choo; Sungchun Jang; Sang-Hyeok Chu; Sungwoo Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. - Woo-Rham Bae; Borivoje Nikolic; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. - Min-Seong Choo; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong (A-SSCC, 2018)

A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS. - Young-Ha Hwang; Yoonho Song; Jun-Eun Park; Deog-Kyoon Jeong (A-SSCC, 2018)

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Sang-Hyeok Chu; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (BCICTS, 2018)

Adiabatically driven touch controller analog front-end for ultra-thin displays. - Jiheon Park; Young-Ha Hwang; Jonghyun Oh; Jun-Eun Park; Deog-Kyoon Jeong (CICC, 2018)

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS. - Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Gyu-Seob Jeong; Daehyun Koh; Seong Ho Park; Deog-Kyoon Jeong (ISLPED, 2018)

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Deog-Kyoon Jeong (VLSI Circuits, 2018)

A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit. - Jun-Eun Park; Deog-Kyoon Jeong (VLSI Circuits, 2018)

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. - Kwanseo Park; Woo-Rham Bae; Jinhyung Lee; Jeongho Hwang; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2018)

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Han-Gon Ko; Jinhyung Lee; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS. - Hong-Seok Choi; Jeongho Hwang; Gyu-Seob Jeong; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. - Min-Seong Choo; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Woo-Rham Bae; Jun-Eun Park; Chang-Soo Yoon; Jungmin Yoon; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 20 k-to-100kS/s Sub-µW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-µm CMOS. - Young-Ha Hwang; Jun-Eun Park; Yoonho Song; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. - Gyu-Seob Jeong; Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Daehyun Koh; Daeyoung Yun; Jinhyung Lee; Kwanseo Park; Han-Gon Ko; Kwangho Lee; Jiho Joo; Gyungock Kim; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. - Mino Kim; Joo-Hyung Chae; Sungphil Choi; Gi-Moon Hong; Hyeongjun Ko; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE. - Jinhyung Lee; Kwanseo Park; Kwangho Lee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Jaeduk Han; Deog-Kyoon Jeong (IEEE Trans. Ind. Electron., 2018)

A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation. - Hye-Yoon Joo; Deog-Kyoon Jeong (A-SSCC, 2019)

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. - Moon-Chul Choi; Haram Ju; Han-Gon Ko; Deog-Kyoon Jeong (ICEIC, 2019)

A $4.7 mu mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS. - Jonghyun Oh; Jun-Eun Park; Deog-Kyoon Jeong (ICEIC, 2019)

An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC. - Young-Ha Hwang; Jonghyun Oh; Jiheon Park; Yoonho Song; Jung-Hun Park; Jun-Eun Park; Deog-Kyoon Jeong (ESSCIRC, 2019)

A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode. - Jiheon Park; Young-Ha Hwang; Jonghyun Oh; Yoonho Song; Jun-Eun Park; Deog-Kyoon Jeong (ISLPED, 2019)

A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time. - Minho Choi; Chan-Ho Kye; Jonghyun Oh; Min-Seong Choo; Deog-Kyoon Jeong (ISSCC, 2019)

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. - Jeongho Hwang; Hyungrok Do; Hong-Seok Choi; Gyu-Seob Jeong; Daehyun Koh; Sungwoo Kim 001; Deog-Kyoon Jeong (OFC, 2019)

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. - Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Gyu-Seob Jeong; Daehyun Koh; Kwanseo Park; Sungwoo Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. - Han-Gon Ko; Soyeong Shin; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Hae-Kang Jung; Doobock Lee; Suhwan Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. - Jinhyung Lee; Kwangho Lee; Hyojun Kim; Byungmin Kim; Kwanseo Park; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. - Kwanseo Park; Kwangho Lee; Sung-Yong Cho; Jinhyung Lee; Jeongho Hwang; Min-Seong Choo; Deog-Kyoon Jeong (VLSI Circuits, 2019)

Reference Spur Reduction Techniques for a Phase-Locked Loop. - Han-Gon Ko; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Access, 2019)

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors. - Jun-Eun Park; Young-Ha Hwang; Deog-Kyoon Jeong (IEEE Access, 2019)

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. - Min-Seong Choo; Kwanseo Park; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2019)

A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen. - Jiheon Park; Young-Ha Hwang; Jonghyun Oh; Yoonho Song; Jun-Eun Park; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2019)

A Noise-Immunity-Enhanced Analog Front-End for $36 times64$ Touch-Screen Controllers With 20- $ text{V}_{ text{PP}}$ Noise Tolerance at 100 kHz. - Jun-Eun Park; Jiheon Park; Young-Ha Hwang; Jonghyun Oh; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2019)

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. - Moon-Chul Choi; Deog-Kyoon Jeong; Sung-Yong Cho; Minkyo Shim; Byungmin Kim; Han-Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. - Min-Seong Choo; Yeonggeun Song; Sung-Yong Cho; Han-Gon Ko; Kwanseo Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Modulo-FIR Equalizer for Wireline Communications. - Gyu-Seob Jeong; Byungjun Kang; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. - Tae Jun Ham; Sungjun Jung; Seonghak Kim; Young H. Oh; Yeonhong Park; Yoonho Song; Jung-Hun Park; Sanghee Lee 002; Kyoung Park; Jae W. Lee; Deog-Kyoon Jeong (HPCA, 2020)

A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface. - Woosong Jung; Jinhyung Lee; Kwangho Lee; Hyojun Kim; Deog-Kyoon Jeong (ISOCC, 2020)

An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference. - Hyojun Kim; Jun-Eun Park; Deog-Kyoon Jeong (ISOCC, 2020)

Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS. - Daehyun Koh; Dainel Jeong; Jeongho Hwang; Deog-Kyoon Jeong (ISOCC, 2020)

A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS. - Jung-Woo Sull; Hyungrok Do; Deog-Kyoon Jeong (ISOCC, 2020)

18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor. - Minho Choi; Deog-Kyoon Jeong (ISSCC, 2020)

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. - Han-Gon Ko; Soyeong Shin; Jonghyun Oh; Kwanseo Park; Deog-Kyoon Jeong (ISSCC, 2020)

25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density. - Jonghyun Oh; Jun-Eun Park; Young-Ha Hwang; Deog-Kyoon Jeong (ISSCC, 2020)

32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement. - Jun-Eun Park; Jeongho Hwang; Jonghyun Oh; Deog-Kyoon Jeong (ISSCC, 2020)

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. - Kwanseo Park; Minkyo Shim; Han-Gon Ko; Deog-Kyoon Jeong (ISSCC, 2020)

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. - Soyeong Shin; Han-Gon Ko; Sungchun Jang; Dongkyun Kim; Deog-Kyoon Jeong (ISSCC, 2020)

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. - Moon-Chul Choi; Han-Gon Ko; Jonghyun Oh; Hye-Yoon Joo; Kwangho Lee; Deog-Kyoon Jeong (VLSI Circuits, 2020)

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference. - Jinhyung Lee; Kwangho Lee; Hyojun Kim; Byungmin Kim; Kwanseo Park; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2020)

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage. - Jungmin Yoon; Hyungrok Do; Daehyun Koh; Seunghan Oak; Junphyo Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2020)

A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS. - Hyungrok Do; Jeongho Hwang; Hong-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. - Jeongho Hwang; Sang-Hyeok Chu; Gyu-Seob Jeong; Yeojoon Youn; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. - Sangyoon Lee 006; Han-Gon Ko; Joo-Hyung Chae; Soyeong Shin; Jaekwang Yun; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme. - Jonghyun Oh; Jun-Eun Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. - Soyeong Shin; Han-Gon Ko; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Doobock Lee; Hae-Kang Jung; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. - Hye-Yoon Joo; Jinhyung Lee; Haram Ju; Han-Gon Ko; Jungmin Yoon; Byungjun Kang; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. - Chan-Ho Kye; Han-Gon Ko; Jinhyung Lee; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS. - Hyungrok Do; Jung-Woo Sull; Seunghyun Lee; Kwangho Lee; Deog-Kyoon Jeong (A-SSCC, 2021)

A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. - Haram Ju; Kwangho Lee; Woosong Jung; Deog-Kyoon Jeong (A-SSCC, 2021)

A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. - Kwangho Lee; Woosong Jung; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong (A-SSCC, 2021)

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. - Woonghee Lee 005; Minkyo Shim; Yunhee Lee; Heejin Yang; Han-Gon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (ESSCIRC, 2021)

A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS. - Hong-Seok Choi; Seungha Roh; Sanghee Lee 002; Jung-Hoon Park; Kwanghoon Lee; Young-Ha Hwang; Deog-Kyoon Jeong (ISOCC, 2021)

A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver. - Yunhee Lee; Woonghee Lee 005; Minkyo Shim; Deog-Kyoon Jeong (ISOCC, 2021)

A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS. - Seungha Roh; Moon-Chul Choi; Deog-Kyoon Jeong (ISOCC, 2021)

A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling. - Minkyo Shim; Woonghee Lee 005; Yunhee Lee; Deog-Kyoon Jeong (ISOCC, 2021)

Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver. - Daeho Yun; Deog-Kyoon Jeong (ISOCC, 2021)

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. - Byungjun Kang; Gyu-Seob Jeong; Jeongho Hwang; Kwanseo Park; Hyungrok Do; Hyojun Kim; Han-Gon Ko; Moon-Chul Choi; Deog-Kyoon Jeong (IEEE Access, 2021)

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. - Min-Seong Choo; Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Kwanseo Park; Jinhyung Lee; Soyeong Shin; Hankyu Chi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2021)

A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. - Kwanseo Park; Kwangho Lee; Sung-Yong Cho; Jinhyung Lee; Jeongho Hwang; Min-Seong Choo; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2021)

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. - Kwangho Lee; Hyojun Kim; Woosong Jung; Jinhyung Lee; Haram Ju; Kwanseo Park; Ook Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. - Chang-Soo Yoon; Han-Gon Ko; Byung-Jun Kang; Jung-Woo Sull; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. - Yeonggeun Song; Kyoungjoon Ha; Han-Gon Ko; Min-Seong Choo; Deog-Kyoon Jeong (ESSCIRC, 2022)

A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE. - Kyungmin Baek; Kahyun Kim; Deog-Kyoon Jeong (ISOCC, 2022)

Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy Applications. - Yoonho Song; Eunseo Kim; Deog-Kyoon Jeong (ISOCC, 2022)

A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration. - Hyojun Kim; Hyeong-Seok Oh; Woosong Jung; Yoonho Song; Jonghyun Oh; Deog-Kyoon Jeong (ISSCC, 2022)

0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. - Yunhee Lee; Woonghee Lee 005; Minkyo Shim; Soyeong Shin; Woo-Seok Choi; Deog-Kyoon Jeong (VLSI Technology and Circuits, 2022)

A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. - Jung-Hun Park; Kwang-Hoon Lee; Yongjae Lee; Jung-Woo Sull; Yoonho Song; Sanghee Lee 002; Hyeonseok Lee; Hoyeon Cho; Jonghyun Oh; Han-Gon Ko; Deog-Kyoon Jeong (VLSI Technology and Circuits, 2022)

A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. - Young-Ha Hwang; Jonghyun Oh; Woo-Seok Choi; Deog-Kyoon Jeong; Jun-Eun Park (IEEE J. Solid State Circuits, 2022)

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. - Haram Ju; Kwangho Lee; Kwanseo Park; Woosong Jung; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. - Hyojun Kim; Woosong Jung; Kwandong Kim; Sungwoo Kim 001; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. - Kwanseo Park; Minkyo Shim; Han-Gon Ko; Borivoje Nikolic; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. - Moon-Chul Choi; Sanghee Lee 002; Seungha Roh; Kwangho Lee; Jonghyun Oh; Sungwoo Kim 001; Kwandong Kim; Woo-Seok Choi; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. - Woonghee Lee 005; Minkyo Shim; Yunhee Lee; Heejin Yang; Soyeong Shin; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector. - Seungha Roh; Kwangho Lee; Minkyo Shim; Moon-Chul Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. - Soyeong Shin; Yongjae Lee; Jiheon Park; Jihyo Kang; Kyunghoon Kim; Dae-Han Kwon; Sangkwon Lee; Jieun Jang; Joo-Hwan Cho; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. - Yeonggeun Song; Han-Gon Ko; Changhyun Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS. - Jung-Woo Sull; Soyeong Shin; Jonghyun Oh; Kwang-Hoon Lee; Jihee Kim; Jung-Hun Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. - Daeho Yun; Eonhui Lee; Woosong Jung; Kahyun Kim; Kyung-Min Beak; Jihee Kim; Hyun Bae Lee; Byeongseon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques. - Young-Ha Hwang; Yoonho Song; Jun-Eun Park; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. - Daeho Yun; Minsu Park; Kahyun Kim; Kyungmin Baek; Eonhui Lee; Woo-Seok Choi; Deog-Kyoon Jeong (A-SSCC, 2023)

A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces. - Woosong Jung; Hyojun Kim; Yeonggeun Song; Kwang-Hoon Lee; Deog-Kyoon Jeong (CICC, 2023)

A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector. - Woosong Jung; Minkyo Shim; Seungha Roh; Deog-Kyoon Jeong (ISCAS, 2023)

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. - Kahyun Kim; Daeho Yun; Kyungmin Baek; Woo-Seok Choi; Deog-Kyoon Jeong (ISCAS, 2023)

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. - Jung-Hun Park; Hyeonseok Lee; Hoyeon Cho; Sanghee Lee 002; Kwang-Hoon Lee; Han-Gon Ko; Deog-Kyoon Jeong (ISSCC, 2023)

An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS. - Jung-Woo Sull; Minkyo Shim; Jung-Hun Park; Sanghee Lee 002; Deog-Kyoon Jeong (MWSCAS, 2023)

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link. - Minkyo Shim; Woonghee Lee 005; Yunhee Lee; Kwanseo Park; Deog-Kyoon Jeong (IEEE Access, 2023)

An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector. - Jonghyun Oh; Young-Ha Hwang; Jun-Eun Park; Mingoo Seok; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2023)

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation. - Minkyo Shim; Kwang-Hoon Lee; Seungha Roh; Kwanseo Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. - Woosong Jung; Kwangho Lee; Kwanseo Park; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2023)

An 80-Gb/s PAM-4 Simultaneous Bidirectional Transceiver With Hybrid Adaptation Scheme. - Yunhee Lee; Minkyo Shim; Seungha Roh; Woonghee Lee 005; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications. - Young-Ha Hwang; Jun Wang; Deog-Kyoon Jeong; Jun-Eun Park (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS. - Sanghee Lee 002; Byungjun Kang; Woogeun Rhee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. - Kwang-Hoon Lee; Jung-Hun Park; Yongjae Lee; Yeonggeun Song; Seungha Roh; Minkyo Shim; Yoonho Song; Woosong Jung; Young-Ha Hwang; Jonghyun Oh; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology. - Hong-Seok Choi; Jae-Geon Lee; Kwang-Ho Lee; Daehyun Koh; Jung-Woo Sull; Hyungrok Do; Chan-Ho Kye; Deog-Kyoon Jeong; Min-Seong Choo (A-SSCC, 2024)

A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS. - Minkyo Shim; Seungha Roh; Yunhee Lee; Jung-Woo Sull; Deog-Kyoon Jeong; Kwanseo Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR. - Seungha Roh; Minkyo Shim; Yoojin Jung; Deog-Kyoon Jeong; Kwanseo Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation. - Hyun-Seok Choi; Sunki Cho; Sanghee Lee 002; Hyeri Roh; Jeongeun Song; Honggyoo Ahn; Jihee Kim; Minchang Kim; Hankyu Chi; Deog-Kyoon Jeong; Woo-Seok Choi (CICC, 2025)

A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL. - Kyungmin Baek; Jiho Kim; Kahyun Kim; Deog-Kyoon Jeong; Min-Seong Choo (IEEE Trans. Very Large Scale Integr. Syst., 2025)