WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. - Deokjin Joo; Taewhan Kim 001 (DAC, 2011)

Clock design techniques considering circuit reliability. - YongHwan Kim; Minseok Kang; Kyoung-Hwan Lim; Sangdo Park; Deokjin Joo; Taewhan Kim 001 (ISOCC, 2011)

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. - Hochang Jang; Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Design Methodologies for Reliable Clock Networks. - Deokjin Joo; Minseok Kang; Taewhan Kim 001 (J. Comput. Sci. Eng., 2012)

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. - Juyeon Kim; Deokjin Joo; Taewhan Kim 001 (DAC, 2013)

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. - Kyoung-Hwan Lim; Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. - Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. - Deokjin Joo; Taewhan Kim 001 (ASP-DAC, 2016)

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. - Juyeon Kim; Deokjin Joo; Taewhan Kim 001 (Integr., 2016)

Kapre: On-GPU Audio Preprocessing Layers for a Quick Implementation of Deep Neural Network Models with Keras. - Keunwoo Choi; Deokjin Joo; Juho Kim (CoRR, 2017)

Clock buffer polarity assignment under useful skew constraints. - Deokjin Joo; Taewhan Kim 001 (Integr., 2017)