Current sensing for built-in testing of CMOS circuits. - Derek B. I. Feltham; Phil Nigh; L. Richard Carley; Wojciech Maly (ICCD, 1988)

Physically realistic fault models for analog CMOS neural networks. - Derek B. I. Feltham; Wojciech Maly (IEEE J. Solid State Circuits, 1991)

Design for testability view on placement and routing. - Derek B. I. Feltham; Jitendra Khare; Wojciech Maly (EURO-DAC, 1992)

Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits. - Jitendra Khare; Derek B. I. Feltham; Wojciech Maly (IEEE J. Solid State Circuits, 1993)

Smart-Substrate Multichip-Module Systems. - Wojciech Maly; Derek B. I. Feltham; Anne E. Gattiker; Mark D. Hobaugh; Kenneth Backus; Michael E. Thomas (IEEE Des. Test Comput., 1994)