A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. - Peter Kuoyuan Hsu; Yukit Tang; Derek Tao; Ming-Chieh Huang; Min-Jer Wang; C. H. Wu; Quincy Lee (VLSIC, 2012)

A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology. - Nick Zhang; Young Suk Kim; Peter Hsu; Samsoo Kim; Derek Tao; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)