Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. - Derek Wright; Manoj Sachdev (ITC, 2003)

Co-Scheduling of Computation and Data on Computer Clusters. - Alexandru Romosan; Doron Rotem; Arie Shoshani; Derek Wright (SSDBM, 2005)

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. - Nitin Mohan; Wilson Fung; Derek Wright; Manoj Sachdev (CICC, 2006)

Design techniques and test methodology for low-power TCAMs. - Nitin Mohan; Wilson Fung; Derek Wright; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers. - Nitin Mohan; Wilson Fung; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. - Dhruv Patel 002; Derek Wright; Manoj Sachdev (ETS, 2018)

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop. - Yugal Kishore Maheshwari; Kleber Stangherlin; Derek Wright; Manoj Sachdev (ICECS, 2021)

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)