The case for registered routing switches in field programmable gate arrays. - Deshanand P. Singh; Stephen Dean Brown (FPGA, 2001)

Integrated retiming and placement for field programmable gate arrays. - Deshanand P. Singh; Stephen Dean Brown (FPGA, 2002)

Constrained clock shifting for field programmable gate arrays. - Deshanand P. Singh; Stephen Dean Brown (FPGA, 2002)

Incremental placement for layout driven optimizations on FPGAs. - Deshanand P. Singh; Stephen Dean Brown (ICCAD, 2002)

Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. - Deshanand P. Singh; Terry P. Borer; Stephen Dean Brown (VLSI, 2003)

The Quartus University Interface Program: enabling advanced FPGA research. - Shawn Malhotra; Terry P. Borer; Deshanand P. Singh; Stephen Dean Brown (FPT, 2004)

Two-stage physical synthesis for FPGAs. - Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (CICC, 2005)

FPGA technology mapping: a study of optimality. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (DAC, 2005)

Incremental retiming for FPGA physical synthesis. - Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (DAC, 2005)

FPGA PLB Evaluation using Quantified Boolean Satisfiability. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (FPL, 2005)

Post-Placement BDD-Based Decomposition for FPGAs. - Valavan Manohararajah; Deshanand P. Singh; Stephen Dean Brown (FPL, 2005)

FPGA Logic Synthesis Using Quantified Boolean Satisfiability. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (SAT, 2005)

Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. - Gordon R. Chiu; Deshanand P. Singh; Valavan Manohararajah; Stephen Dean Brown (ICCAD, 2006)

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (SLIP, 2006)

Incremental placement for structured ASICs using the transportation problem. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (VLSI-SoC, 2007)

An area-efficient timing closure technique for FPGAs using Shannon's expansion. - Deshanand P. Singh; Stephen Dean Brown (Integr., 2007)

FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. - Andrew C. Ling; Deshanand P. Singh; Stephen Dean Brown (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. - Valavan Manohararajah; Gordon R. Chiu; Deshanand P. Singh; Stephen Dean Brown (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. - Doris Chen; Deshanand P. Singh; Jeffrey Chromczak; David M. Lewis; Ryan Fung; David Neto; Vaughn Betz (FPGA, 2010)

Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs). - Doris Chen; Deshanand P. Singh (FPL, 2010)

Line-level incremental resynthesis techniques for FPGAs. - Doris Chen; Deshanand P. Singh (FPGA, 2011)

Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. - Doris Chen; Deshanand P. Singh (FPL, 2012)

From opencl to high-performance hardware on FPGAS. - Tomasz S. Czajkowski; Utku Aydonat; Dmitry Denisenko; John Freeman; Michael Kinsner; David Neto; Jason Wong; Peter Yiannacouras; Deshanand P. Singh (FPL, 2012)

Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. - Doris Chen; Deshanand P. Singh (ASP-DAC, 2013)

Harnessing the power of FPGAs using altera's OpenCL compiler. - Deshanand P. Singh; Tomasz S. Czajkowski; Andrew C. Ling (FPGA, 2013)

Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications. - Doris Chen; Deshanand P. Singh (ACM Trans. Archit. Code Optim., 2013)

Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL. - Mohamed S. Abdelfattah; Andrei Hagiescu; Deshanand P. Singh (IWOCL, 2014)

High-Level Design Tools for Floating Point FPGAs. - Deshanand P. Singh; Bogdan Pasca 001; Tomasz S. Czajkowski (FPGA, 2015)

OpenCL. - Deshanand P. Singh; Peter Yiannacouras (FPGAs for Software Programmers, 2016)

A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. - Yuan Meng 001; Michael Kinsner; Deshanand P. Singh; Mahesh A. Iyer; Viktor K. Prasanna (CoRR, 2023)

PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. - Yuan Meng 001; Michael Kinsner; Deshanand P. Singh; Mahesh A. Iyer; Viktor K. Prasanna (CF, 2024)

Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. - Ahmed F. AbouElhamayed; Susanne Balle; Deshanand P. Singh; Mohamed S. Abdelfattah (DAC, 2024)

Primate: A Framework to Automatically Generate Soft Processors for Network Applications. - Rui Ma; Jia-Ching Hsu; Ali Mansoorshahi; Joseph Garvey; Michael Kinsner; Deshanand P. Singh; Derek Chiou (IEEE Comput. Archit. Lett., 2024)