Layout Validation Using Graph Grammar and Generation of Yard Specific Safety Properties for Railway Interlocking Verification. - Devleena Ghosh; Chittaranjan Mandal 002 (APSEC, 2015)

A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization. - Gargi Roy; Devleena Ghosh; Chittaranjan Mandal 002 (T4E, 2015)

Aiding Teaching of Logic Design and Computer Organization through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool. - Gargi Roy; Devleena Ghosh; Chittaranjan Mandal 002; Indraneel Mitra (T4E, 2015)

Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan. - Arindam Das; Manoj Kumar Gangwar; Devleena Ghosh; Chittaranjan Mandal 002; Anirban Sengupta; M. Mubashshir Waris (IEEE Trans. Intell. Transp. Syst., 2021)

Clustering Based Parameter Estimation of Thyroid Hormone Pathway. - Devleena Ghosh; Chittaranjan Mandal 002 (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

Harnessing Multiple BMC Engines Together for Efficient Formal Verification. - Devleena Ghosh; Sumana Ghosh; Raj Kumar Gajavelly; Ansuman Banerjee (MEMOCODE, 2023)

MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together. - Devleena Ghosh; Sumana Ghosh; Ansuman Banerjee; Raj Kumar Gajavelly; Sudhakar Surendran (ACM Trans. Design Autom. Electr. Syst., 2024)

SMT based parameter identifiable combination detection for non-linear continuous and hybrid dynamics. - Devleena Ghosh; Chittaranjan Mandal 002 (Formal Aspects Comput., 2024)

Subject-Specific Dosage Estimation for Primary Hypothyroidism Using Sparse Data. - Devleena Ghosh; Chittaranjan Mandal 002 (J. Comput. Biol., 2025)