A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers. - Deyi Pi; Byung-Kwan Chun; Payam Heydari (CICC, 2007)

Theoretical Analysis of Novel Multi-Order LC Oscillators. - Fred Tzeng; Deyi Pi; Amin Q. Safarian; Payam Heydari (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (ISSCC, 2009)

A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End. - Fred Tzeng; Amin Jahanian; Deyi Pi; Payam Heydari (IEEE J. Solid State Circuits, 2009)

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (IEEE J. Solid State Circuits, 2010)

A 19 mW/lane Serdes transceiver for SFI-5.1 application. - Siavash Fallahi; Delong Cui; Deyi Pi; Rose Zhu; Greg Unruh; Marcel Lugthart; Afshin Momtaz (CICC, 2011)

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (ISSCC, 2011)

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (IEEE J. Solid State Circuits, 2011)

A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design. - Deyi Pi; Byung-Kwan Chun; Payam Heydari (IEEE J. Solid State Circuits, 2011)

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Tamer A. Ali 001; Nick Huang; Wei Zhang; et al. (ISSCC, 2012)

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Wei Zhang; Tamer A. Ali 001; Nick Huang; et al. (IEEE J. Solid State Circuits, 2012)

A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Deyi Pi; Anand Vasani; Zhi Chao Huang; Burak Çatli; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2013)