Network on Chip for Parallel DSP Architectures. - Yuanli Jing; Xiaoya Fan; Deyuan Gao; Jian Hu (ICESS, 2005)

Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip. - Danghui Wang; Xiaoya Fan; Deyuan Gao; Shengbing Zhang; Jianfeng An (ICESS, 2005)

Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion. - Hangpei Tian; Deyuan Gao; Wu Wei; Xiaoya Fan; Yian Zhu (FCCM, 2008)

Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding. - Hangpei Tian; Deyuan Gao; Deli Wang; Yian Zhu; Shengbing Zhang; Jing Wang (MUE, 2008)

Gaining Flexibility and Performance of Computing Using Tailored Instruction Set and Reconfigurable Architecture. - Hangpei Tian; Deyuan Gao; Yian Zhu; Deli Wang; Jing Wang (MUE, 2008)

A 71ps-resolution Multi-channel CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications. - Wu Gao; Christine Hu-Guo; Nicolas Ollivier-Henry; Yann Hu; Deyuan Gao; Tingcun Wei (IMAGAPP, 2009)

Global Prefetcher Aggressiveness Control for Chip-Multiprocessor. - Limin Han; Deyuan Gao; Xiaoya Fan; Liwen Shi; Jianfeng An (CIS, 2011)

Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems. - Wu Gao; Deyuan Gao; Christine Hu-Guo; Yann Hu (IEEE Trans. Instrum. Meas., 2011)

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router. - Xianglong Ren; Deyuan Gao; Xiaoya Fan; Jianfeng An; Tao Yao (CIT, 2012)

Three-Operand Floating-Point Adder. - Tao Yao; Deyuan Gao; Xiaoya Fan; Xianglong Ren (CIT, 2012)

Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation. - Tao Yao; Deyuan Gao; Xiaoya Fan; Jari Nurmi (ASAP, 2013)

Integrating internet of things and mixed reality to teach performance-based architectural design: a case study of shading devices. - Shenghuan Zhao; Qiang Pan; Deyuan Gao; Jiqiu Cheng (Educ. Inf. Technol., 2022)