Measuring the instability of AC arc discharges. - Mazin Kadhim; Dhamin Al-Khalili; Imaddin Al-Bazz (Microprocess. Microsystems, 1981)

An algorithm for polygon conversion to boxes for VLSI layouts. - Asim J. Al-Khalili; Dhamin Al-Khalili; K. Ammar (Integr., 1988)

A module generator for optimized CMOS buffers. - Asim J. Al-Khalili; Yong Zhu; Dhamin Al-Khalili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Testability analysis and fault modeling of BiCMOS circuits. - Dhamin Al-Khalili; Côme Rozon; B. Stewart (J. Electron. Test., 1992)

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. - Michael Ogbonna Esonu; Dhamin Al-Khalili; Côme Rozon (VLSI Design, 1994)

A floating-point systolic array processing element with serial communication and built-in self-test. - T. C. Davies; Dhamin Al-Khalili; Valek Szwarc (J. VLSI Signal Process., 1994)

Design techniques for fault-tolerant systolic arrays. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri; Dhamin Al-Khalili (J. VLSI Signal Process., 1995)

Energy delay analysis of partial product reduction methods for parallel multiplier implementation. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISLPED, 1996)

A Low Power Approach to Floating Point Adder Design. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ICCD, 1997)

Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISLPED, 1997)

VHDL Modelling and Analysis of Fault Secure Systems. - Jason Coppens; Dhamin Al-Khalili; Côme Rozon (DATE, 1998)

Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. - Dhamin Al-Khalili; Saman Adham; Côme Rozon; Moazzem Hossain; Douglas Racz (DFT, 1998)

A Low Power Floating Point Accumulator. - R. V. K. Pillai; Asim J. Al-Khalili; Dhamin Al-Khalili (VLSI Design, 1998)

An IEEE Compliant Floating Point MAF. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (VLSI, 1999)

Power implications of precision limited arithmetic in floating point FIR filters. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISCAS (1), 1999)

Synthesis of low-power CMOS circuits using hybrid topologies. - Michael Gallant; Dhamin Al-Khalili (Integr., 1999)

Behavioural synthesis of low power floating point CORDIC processors. - Joe Costello; Dhamin Al-Khalili (ICECS, 2000)

Comparing defect coverage for current-mode logic and CMOS VLSI cells. - Côme Rozon; Dhamin Al-Khalili; Saman Adham; Douglas Racz (ICECS, 2000)

A CAD tool for first hand CMOS circuit selection. - P. Sun; A. J. Al-Khalili; Dhamin Al-Khalili (ICECS, 2000)

Comprehensive defect analysis and testability of current-mode logic circuits. - Saman Adham; Dhamin Al-Khalili; Côme Rozon; Douglas Racz (ISCAS, 2000)

Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. - Donald B. Shaw; Dhamin Al-Khalili; Côme Rozon (ICCAD, 2001)

Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. - Donald B. Shaw; Dhamin Al-Khalili; Côme Rozon (ISCAS (5), 2001)

Low power floating point MAFs-a comparative study. - R. V. K. Pillai; S. Y. A. Shah; A. J. Al-Khalili; Dhamin Al-Khalili (ISSPA, 2001)

A Low Power Approach to Floating Point Adder Design for DSP Applications. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili; S. Y. A. Shah (J. VLSI Signal Process., 2001)

A low power direct digital frequency synthesizer with 60 dBc spectral purity. - J. M. Pierre Langlois; Dhamin Al-Khalili (ACM Great Lakes Symposium on VLSI, 2002)

Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. - J. M. Pierre Langlois; Dhamin Al-Khalili (ISCAS (5), 2002)

Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models. - Donald B. Shaw; Dhamin Al-Khalili; Côme Rozon (Integr., 2002)

Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation. - J. M. Pierre Langlois; Dhamin Al-Khalili; Robert J. Inkol (J. VLSI Signal Process., 2002)

Adaptive wire adjustment for bounded skew Clock Distribution Network. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (ASP-DAC, 2003)

Low power direct digital frequency synthesizers in 0.18 μm CMOS. - J. M. Pierre Langlois; Dhamin Al-Khalili (CICC, 2003)

IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs. - Donald B. Shaw; Dhamin Al-Khalili; Côme Rozon (IEEE Trans. Computers, 2003)

Technology-portable analytical model for DSM CMOS inverter transition-time estimation. - Adnan Kabbani; Dhamin Al-Khalili; Asim J. Al-Khalili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation. - J. M. Pierre Langlois; Dhamin Al-Khalili (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Clock tree tuning using shortest paths polygon. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili (SoCC, 2004)

Leakage power dissipation in UDSM logic gates. - Hussam Al-Hertani; Dhamin Al-Khalili; Côme Rozon (Circuits, Signals, and Systems, 2005)

Delay analysis of CMOS gates using modified logical effort model. - Adnan Kabbani; Dhamin Al-Khalili; Asim J. Al-Khalili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Accurate Total Static Leakage Current Estimation in Transistor Stacks. - Hussam Al-Hertani; Dhamin Al-Khalili; Côme Rozon (AICCSA, 2006)

An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (AICCSA, 2006)

Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini; J. M. Pierre Langlois (SoCC, 2006)

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. - Donald B. Shaw; Dhamin Al-Khalili; Côme Rozon (Integr., 2006)

Carry-free approximate squaring functions with O(n) complexity and O(1) delay. - J. M. Pierre Langlois; Dhamin Al-Khalili (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (ASAP, 2007)

Optimised realisations of large integer multipliers and squarers using embedded blocks. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (IET Comput. Digit. Tech., 2007)

Efficient FPGA implementation of complex multipliers using the logarithmic number system. - Man Yan Kong; J. M. Pierre Langlois; Dhamin Al-Khalili (ISCAS, 2008)

UDSM subthreshold leakage model for NMOS transistor stacks. - Hussam Al-Hertani; Dhamin Al-Khalili; Côme Rozon (Microelectron. J., 2008)

Two level decomposition based matrix multiplication for FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (ICECS, 2009)

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (Int. J. Reconfigurable Comput., 2009)

Pattern-Driven Clock Tree Routing with Via Minimization. - Ali M. Farhangi; Asim J. Al-Khalili; Dhamin Al-Khalili (ISVLSI, 2010)

FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. - Shuli Gao; Noureddine Chabini; Dhamin Al-Khalili; J. M. Pierre Langlois (J. Signal Process. Syst., 2010)

A CNFET-based characterization framework for digital circuits. - Jacques Laurent Athow; Côme Rozon; Dhamin Al-Khalili; J. M. Pierre Langlois (ICECS, 2011)

Cell stack length using an enhanced logical effort model for a library-free paradigm. - Hisham El-Masry; Dhamin Al-Khalili (ICECS, 2011)

Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (ICECS, 2011)

Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (IPDPS Workshops, 2011)

An improved BCD adder using 6-LUT FPGAs. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini (NEWCAS, 2012)

Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs. - Farid Moshgelani; Dhamin Al-Khalili; Côme Rozon (NEWCAS, 2012)

Asymmetric large size multipliers with optimised FPGA resource utilisation. - Shuli Gao; Dhamin Al-Khalili; Noureddine Chabini; J. M. Pierre Langlois (IET Comput. Digit. Tech., 2012)

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs. - Farid Moshgelani; Dhamin Al-Khalili; Côme Rozon (J. Electr. Comput. Eng., 2013)

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. - Shuli Gao; Dhamin Al-Khalili; J. M. Pierre Langlois; Noureddine Chabini (CCECE, 2017)

Comprehensive investigation of gate oxide short in FinFETs. - Roya Dibaj; Dhamin Al-Khalili; Maitham Shams (VTS, 2017)

Efficient Realization of BCD Multipliers Using FPGAs. - Shuli Gao; Dhamin Al-Khalili; J. M. Pierre Langlois; Noureddine Chabini (Int. J. Reconfigurable Comput., 2017)

Gate Oxide Short Defect Model in FinFETs. - Roya Dibaj; Dhamin Al-Khalili; Maitham Shams (J. Electron. Test., 2018)

FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations. - Waqas Gul; Maitham Shams; Dhamin Al-Khalili (ISCAS, 2023)