Novel Gate Tracking and N-well Control Circuit for $2 times text{VDD}$ Tolerant I/O Buffer. - Dharmaray Nedalgi; Saroja V. Siddamal (APCCAS, 2021)

$2 times text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability. - Dharmaray Nedalgi; Saroja V. Siddamal (APCCAS, 2021)

High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. - Dharmaray Nedalgi; Saroja V. Siddamal (VLSID, 2021)

Differential receiver with 2 × VDD input signals using 1 × VDD devices. - Dharmaray Nedalgi; Saroja V. Siddamal (Integr., 2022)

Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability. - Dharmaray Nedalgi; Saroja V. Siddamal (J. Circuits Syst. Comput., 2022)

Supply Noise and Peak Current Reduction in High-Speed Output Drivers. - Dharmaray Nedalgi; Lavanya M. N; Saroja V. Siddamal (VLSID, 2023)

2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues. - Dharmaray Nedalgi; Saroja V. Siddamal; S. S. Kerur (Integr., 2024)