Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. - Dheepakkumaran Jayaraman; Edward Flanigan; Spyros Tragoudas (ITC, 2008)

Gating internal nodes to reduce power during scan shift. - Dheepakkumaran Jayaraman; Rajamani Sethuram; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2010)

Scan Shift Power Reduction by Gating Internal Nodes. - Dheepakkumaran Jayaraman; Rajamani Sethuram; Spyros Tragoudas (J. Low Power Electron., 2010)

Occurrence probability analysis of a path at the architectural level. - Dheepakkumaran Jayaraman; Spyros Tragoudas (ISQED, 2011)

Performance validation through implicit removal of infeasible paths of the behavioral description. - Dheepakkumaran Jayaraman; Spyros Tragoudas (ISQED, 2013)

A method to determine the sensitization probability of a non-robustly testable path. - Dheepakkumaran Jayaraman; Spyros Tragoudas (ISQED, 2013)