Methodology for optimizing ESD protection for high speed LVDS based I/Os. - Vishnuram Abhinav; Amitabh Chatterjee; Dheeraj Kumar Sinha; Rajan Singh (VDAT, 2015)

A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach. - Vishnuram Abhinav; Dheeraj Kumar Sinha; Amitabh Chatterjee; Forrest Brewer (VLSID, 2016)

A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET. - Dheeraj Kumar Sinha; Amitabh Chatterjee; Vishnuram Abhinav; Gaurav Trivedi; Victor Koldyaev (VLSID, 2016)

FEM Based Device Simulator for High Voltage Devices. - Ashok Ray; Gaurav Kumar; Sushanta Bordoloi; Dheeraj Kumar Sinha; Pratima Agarwal; Gaurav Trivedi (VDAT, 2017)

SPICE level implementation of physics of filamentation in ESD protection devices. - Dheeraj Kumar Sinha; Amitabh Chatterjee (Microelectron. Reliab., 2017)