Formal verification for analysis and design of reconfigurable controllers for manufacturing systems. - Dhrubajyoti Kalita; Pramod P. Khargonekar (ACC, 2000)

Formal verification for analysis and design of logic controllers for reconfigurable machining systems. - Dhrubajyoti Kalita; Pramod P. Khargonekar (IEEE Trans. Robotics Autom., 2002)

Towards RTL test generation from SystemC TLM specifications. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (HLDVT, 2007)

Coverage-driven automatic test generation for uml activity diagrams. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (ACM Great Lakes Symposium on VLSI, 2008)

Efficient test case generation for validation of UML activity diagrams. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (Des. Autom. Embed. Syst., 2010)

Automatic RTL Test Generation from SystemC TLM Specifications. - Mingsong Chen 001; Prabhat Mishra 001; Dhrubajyoti Kalita (ACM Trans. Embed. Comput. Syst., 2012)