Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. - Dhruv Patel 002; Derek Wright; Manoj Sachdev (ETS, 2018)

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes. - Dhruv Patel 002; Alireza Sharif Bakhtiar; Anthony Chan Carusone (CICC, 2022)

A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes. - Dhruv Patel 002; Alireza Sharif Bakhtiar; Tony Chan Carusone (IEEE J. Solid State Circuits, 2023)