Impedance Profile of a Commercial Power Grid and Test System. - Dhruva Acharyya; Jim Plusquellic (ITC, 2003)

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. - Chintan Patel; Ernesto Staroswiecki; Smita Pawar; Dhruva Acharyya; Jim Plusquellic (J. Electron. Test., 2003)

Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. - Dhruva Acharyya; Jim Plusquellic (VTS, 2005)

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. - Jim Plusquellic; Dhruva Acharyya; Abhishek Singh 001; Mohammad Tehranipoor; Chintan Patel (IEEE Des. Test Comput., 2006)

Rigorous extraction of process variations for 65nm CMOS design. - Wei Zhao; Yu Cao 001; Frank Liu 001; Kanak Agarwal 001; Dhruva Acharyya; Sani R. Nassif; Kevin J. Nowka (ESSCIRC, 2007)

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. - Rouwaida Kanj; Rajiv V. Joshi; Jayakumaran Sivagnaname; Jente B. Kuang; Dhruva Acharyya; Tuyet Nguyen; Chandler McDowell; Sani R. Nassif (ISQED, 2007)

A physical unclonable function defined using power distribution system equivalent resistance variations. - Ryan Helinski; Dhruva Acharyya; Jim Plusquellic (DAC, 2009)

Characterizing within-die variation from multiple supply port IDDQ measurements. - Kanak Agarwal 001; Dhruva Acharyya; Jim Plusquellic (ICCAD, 2009)

Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. - Ryan Helinski; Dhruva Acharyya; Jim Plusquellic (DAC, 2010)

Leveraging existing power control circuits and power delivery architecture for variability measurement. - Dhruva Acharyya; Kanak Agarwal 001; Jim Plusquellic (ITC, 2010)

Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s. - Jim Aarestad; Dhruva Acharyya; Reza M. Rad; Jim Plusquellic (IEEE Trans. Inf. Forensics Secur., 2010)

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. - Jim Aarestad; Charles Lamech; Jim Plusquellic; Dhruva Acharyya; Kanak Agarwal 001 (DAC, 2011)

Measuring within-die spatial variation profile through power supply current measurements. - Jim Plusquellic; Dhruva Acharyya; Kanak Agarwal 001 (ISQED, 2011)

Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. - Dhruva Acharyya; Kosuke Miyao; David Ting; Daniel Lam; Robert Smith; Pete Fitzpatrick; Brian Buras; John Williamson (ITC, 2011)

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. - Raj Chakraborty; Charles Lamech; Dhruva Acharyya; Jim Plusquellic (DAC, 2013)

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. - Jim Aarestad; Jim Plusquellic; Dhruva Acharyya (HOST, 2013)

HELP: A Hardware-Embedded Delay PUF. - Jim Aarestad; Philip Ortiz; Dhruva Acharyya; Jim Plusquellic (IEEE Des. Test, 2013)