A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos (ACM Great Lakes Symposium on VLSI, 2008)

A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos (ISQED, 2008)

Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos (ISQED, 2008)

Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos (ACM Great Lakes Symposium on VLSI, 2009)

Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos (ISQED, 2009)

A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos; Priyadarsan Patra (ISQED, 2009)

A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. - Saraju P. Mohanty; Dhruva Ghai; Elias Kougianos; Bharat Joshi (ISQED, 2009)

Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study. - Dhruva Ghai; Saraju P. Mohanty; Elias Kougianos (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. - Garima Thakral; Saraju P. Mohanty; Dhruva Ghai; Dhiraj K. Pradhan (ACM Great Lakes Symposium on VLSI, 2010)

P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. - Garima Thakral; Saraju P. Mohanty; Dhruva Ghai; Dhiraj K. Pradhan (ISQED, 2010)

A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. - Saraju P. Mohanty; Dhruva Ghai; Elias Kougianos (VLSI Design, 2010)

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. - Garima Thakral; Saraju P. Mohanty; Dhruva Ghai; Dhiraj K. Pradhan (VLSI Design, 2010)

Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study. - Dhruva Ghai; Saraju P. Mohanty; Garima Thakral (ISQED, 2013)

Double gate FinFET based mixed-signal design: A VCO case study. - Dhruva Ghai; Saraju P. Mohanty; Garima Thakral (MWSCAS, 2013)

Comparative analysis of double gate FinFET configurations for analog circuit design. - Dhruva Ghai; Saraju P. Mohanty; Garima Thakral (MWSCAS, 2013)

Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm. - Dhruva Ghai; Saraju P. Mohanty; Garima Thakral (Microelectron. J., 2013)

Variability-aware design of double gate FinFET-based current mirrors. - Dhruva Ghai; Saraju P. Mohanty; Garima Thakral; Oghenekarho Okobiah (ACM Great Lakes Symposium on VLSI, 2014)

Distributed Trust-Based Multiple Attack Prevention for Secure MANETs. - Gurveen Vaseer; Garima Ghai; Dhruva Ghai (iSES, 2018)

Computing in Geographic Information Systems [Book Review]. - Dhruva Ghai (IEEE Consumer Electron. Mag., 2019)

Novel Intrusion Detection and Prevention for Mobile Ad Hoc Networks: A Single- and Multiattack Case Study. - Gurveen Vaseer; Garima Ghai; Dhruva Ghai (IEEE Consumer Electron. Mag., 2019)

Federated Learning. - Niranjan Kumar Ray 001; Deepak Puthal; Dhruva Ghai (IEEE Consumer Electron. Mag., 2021)

A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators. - Sudheer Vishwakarma; Gopal Raut; Narendra Singh Dhakad; Santosh Kumar Vishvakarma; Dhruva Ghai (IFIPIoT (1), 2023)

A Precision-Aware Neuron Engine for DNN Accelerators. - Sudheer Vishwakarma; Gopal Raut; Sonu Jaiswal; Santosh Kumar Vishvakarma; Dhruva Ghai (SN Comput. Sci., 2024)