Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow. - Dhruva S. Hegde; Mandar Datar 001; Manish Prajapati; Sachin B. Patkar; Gaurav Trivedi (VDAT, 2024)

Python-based DSL for generating Verilog model of Synchronous Digital Circuits. - Mandar Datar 001; Dhruva S. Hegde; Vendra Durga Prasad; Manish Prajapati; Neralla Manikanta; Devansh Gupta; Janampalli Pavanija; Pratyush Pare; Akash; Shivam Gupta; Sachin B. Patkar (CoRR, 2024)