Routing in general junctions. - Sanjeev Rao Maddila; Dian Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

An optimum channel routing algorithm in the restricted wire overlap model. - Dian Zhou (Integr., 1990)

Algorithms for VLSI routing - Dian Zhou (1990)

Performance-Driven Interconnect Design Based on Distributed RC Delay Model. - Jason Cong; Kwok-Shing Leung; Dian Zhou (DAC, 1993)

Neighbour State Transition Method for VLSI Optimization Problems. - Dian Zhou; F. Tsui (ICCD, 1993)

Propagation Delay in RLC Interconnection Networks. - D. S. Gao; Dian Zhou (ISCAS, 1993)

A Two-pole Circuit Model for VLSI High-speed Interconnection. - Dian Zhou; S. Su; F. Tsui; D. S. Gao; Jason Cong (ISCAS, 1993)

Preface. - Si-Qing Zheng; Dian Zhou (VLSI Design, 1994)

Optimization of VLSI Allocation. - Zhongli He; Dian Zhou (ISCAS, 1995)

Minimization of chip size and power consumption of high-speed VLSI buffers. - Dian Zhou; Xingya Liu (ISPD, 1997)

An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles. - Haksu Kim; Dian Zhou (ISCAS (6), 1999)

A constraint-based placement refinement method for CMOS analog cell layout. - Xuan Zeng 001; J. Guan; Wenqing Zhao; Pushan Tang; Dian Zhou (ISCAS (6), 1999)

Buffer insertion for clock delay and skew minimization. - Xuan Zeng 001; Dian Zhou; Wei Li (ISPD, 1999)

Parasitic and mismatch modeling for optimal stack generation [in CMOS]. - Xuan Zeng 001; Mingyuan Li; Wenqing Zhao; Pushan Tang; Dian Zhou (ISCAS, 2000)

Efficient implementation of a planar clock routing with thetreatment of obstacles. - Haksu Kim; Dian Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Wire space estimation and routability analysis. - Xiaoyu Song; Qian-Yu Tang; Dian Zhou; Yuke Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. - Xin Li 001; Xuan Zeng 001; Dian Zhou; Xieting Ling (ICCAD, 2001)

Automatic clock tree design with IPs in the system. - Wei Li; Dian Zhou; Haksu Kim; Xuan Zeng 001 (ISCAS (5), 2001)

An efficient balanced truncation realization algorithm for interconnect model order reduction. - Dian Zhou; Wei Li; Wei Cai; Nailong Guo (ISCAS (5), 2001)

A DSP-based turbo codec for 3G communication systems. - Yingtao Jiang; Yiyan Tang; Yuke Wang; Dian Zhou (ICASSP, 2002)

Wavelet method for high-speed clock tree simulation. - Xin Li 001; Xuan Zeng 001; Dian Zhou; Xieting Ling (ISCAS (1), 2002)

Architectural Synthesis of Finite Impulse Response Digital Filters. - Ronald W. Mehler; Dian Zhou (SBCCI, 2002)

Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (ICCAD, 2003)

An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method. - Xuan Zeng 001; Sheng Huang; Yangfeng Su; Dian Zhou (ISCAS (4), 2003)

An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation. - Xuan Zeng 001; Jun Tao 001; Yangfeng Su; Wenbing Chen; Dian Zhou (ISCAS (3), 2003)

Behavioral modeling for analog system-level simulation by wavelet collocation method. - Xin Li 001; Xuan Zeng 001; Dian Zhou; Xieting Ling; Wei Cai 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Satisfiability and integer programming as complementary tools. - Ruiming Li; Dian Zhou; Donglei Du (ASP-DAC, 2004)

Analog circuit behavioral modeling via wavelet collocation method with auto-companding. - Jian Wang; Jun Tao 001; Xuan Zeng 001; Charles C. Chiang; Dian Zhou (ASP-DAC, 2004)

Direct Nonlinear Order Reduction with Variational Analysis. - Lihong Feng; Xuan Zeng 001; Charles C. Chiang; Dian Zhou; Qiang Fang (DATE, 2004)

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. - Xin Zhou; Dian Zhou; Jin Liu 004; Ruiming Li; Xuan Zeng 001; Charles C. Chiang (DATE, 2004)

SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. - Yangfeng Su; Jian Wang; Xuan Zeng 001; Zhaojun Bai; Charles C. Chiang; Dian Zhou (ICCAD, 2004)

Frequency driven repeater insertion for deep submicron. - Nisar Ahmed; Mohammad H. Tehranipour; Dian Zhou; Mehrdad Nourani (ISCAS (5), 2004)

Two-sided projection method in variational equation model order reduction of nonlinear circuits. - Lihong Feng; Xuan Zeng 001; Jiarong Tong; Charles C. Chiang; Dian Zhou (ISCAS (4), 2004)

Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. - Jian Wang; Xuan Zeng 001; Wei Cai 003; Charles C. Chiang; Jiarong Tong; Dian Zhou (ISCAS (5), 2004)

A closed-form phase noise solution for an ideal LC oscillator. - Hua Zhang 019; Jianzhong Zhang 002; Dian Zhou; Jin Liu; Liangjun Jiang; Yan Pan (ISCAS (4), 2004)

Automated Architectural Optimization of Digital FIR Filters. - Ronald W. Mehler; Dian Zhou (VLSI Design, 2004)

Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. - Bang Liu; Xuan Zeng 001; Yangfeng Su; Jun Tao 001; Zhaojun Bai; Charles C. Chiang; Dian Zhou (ASP-DAC, 2005)

A novel wavelet method for noise analysis of nonlinear circuits. - Xuan Zeng 001; Bang Liu; Jun Tao 001; Charles C. Chiang; Dian Zhou (ASP-DAC, 2005)

Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (ISCAS (1), 2005)

Phase noise spectra analysis for LC oscillators. - Hua Zhang 019; Dian Zhou; Yi Hu; Ruiming Li; Jianzhong Zhang 002 (ISCAS (3), 2005)

Integrating advanced reasoning into a SAT solver. - Min Ding 004; Pushan Tang; Dian Zhou (Sci. China Ser. F Inf. Sci., 2005)

Design and Verification of High-Speed VLSI Physical Design. - Dian Zhou; Ruiming Li (J. Comput. Sci. Technol., 2005)

Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. - Hengliang Zhu; Xuan Zeng 001; Wei Cai 003; Dian Zhou (APCCAS, 2006)

Time domain model order reduction by wavelet collocation method. - Xuan Zeng 001; Lihong Feng; Yangfeng Su; Wei Cai 003; Dian Zhou; Charles C. Chiang (DATE, 2006)

A one-shot projection method for interconnects with process variations. - Jun Tao 001; Xuan Zeng 001; Fan Yang 001; Yangfeng Su; Lihong Feng; Wei Cai 003; Dian Zhou; Charles C. Chiang (ISCAS, 2006)

LVS verification across multiple power domains for a quad-core microprocessor. - Wei Li; Daniel Blakely; Scott Van Sooy; Keven Dunn; David Kidd; Robert Rogenmoser; Dian Zhou (ACM Trans. Design Autom. Electr. Syst., 2006)

Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. - Jun Tao 001; Xuan Zeng 001; Wei Cai 003; Yangfeng Su; Dian Zhou; Charles C. Chiang (ASP-DAC, 2007)

A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. - Hengliang Zhu; Xuan Zeng 001; Wei Cai 003; Jintao Xue; Dian Zhou (DATE, 2007)

Traffic Splitting with Network Calculus for Mesh Sensor Networks. - Huimin She; Zhonghai Lu; Axel Jantsch; Li-Rong Zheng 001; Dian Zhou (FGCN (2), 2007)

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. - Fan Yang 001; Xuan Zeng 001; Yangfeng Su; Dian Zhou (ISCAS, 2007)

Solving SAT problem by heuristic polarity decision-making algorithm. - Ming-e Jing; Dian Zhou; Pushan Tang; Xiaofang Zhou; Hua Zhang 019 (Sci. China Ser. F Inf. Sci., 2007)

A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. - Ming-e Jing; Yue Hao; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A current shaping technique to lower phase noise in LC oscillators. - Jian Chen 001; Fredrik Jonsson; Håkan K. Olsson; Li-Rong Zheng 001; Dian Zhou (ICECS, 2008)

An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture. - Shuang Zhao; Wenqing Lu; Chao Lu; Xiaofang Zhou 002; Dian Zhou; Gerald E. Sobelman (ICESS, 2008)

Foundational-circuit-based spice simulation. - Tracey Y. Zhou; Dian Zhou; Hua Zhang 019; Xinyue Niu (ISCAS, 2008)

Low noise amplifier architecture analysis for UWB system. - Peng Wang 092; Fredrik Jonsson; Dian Zhou; Lirong Zheng 001 (SoC, 2008)

PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication. - Peng Wang 092; Hannu Tenhunen; Dian Zhou; Lirong Zheng 001 (SoC, 2008)

Incremental Circuit Simulation Analysis for Design Modification and Verification. - Tracey Y. Zhou; Dian Zhou; Xuan Zeng 001 (ISCAS, 2009)

Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. - Huimin She; Zhonghai Lu; Axel Jantsch; Dian Zhou; Li-Rong Zheng 001 (VTC Spring, 2009)

A Folding Strategy for SAT solvers based on Shannon's expansion theorem. - Siwat Saibua; Po-Yu Kuo; Dian Zhou; Ming-e Jing (SoCC, 2010)

Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations. - Jun Tao 001; Xuan Zeng 001; Wei Cai 003; Yangfeng Su; Dian Zhou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform. - Shuang Zhao; Wenqing Lu; Xiaofang Zhou 002; Dian Zhou; Gerald E. Sobelman (IEICE Trans. Inf. Syst., 2010)

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. - Liulin Zhong; Jiayi Sheng; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Dian Zhou (ASICON, 2011)

Stochastic coverage in event-driven sensor networks. - Huimin She; Zhonghai Lu; Axel Jantsch; Dian Zhou; Li-Rong Zheng 001 (PIMRC, 2011)

A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. - Po-Yu Kuo; Siwat Saibua; Dian Zhou (SoCC, 2011)

Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method. - Siwat Saibua; Liuxi Qian; Dian Zhou (VLSI-SoC, 2011)

Modeling and analysis of Rayleigh fading channels using stochastic network calculus. - Huimin She; Zhonghai Lu; Axel Jantsch; Dian Zhou; Li-Rong Zheng 001 (WCNC, 2011)

A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification. - Tracey Y. Zhou; Hang Liu; Dian Zhou; Tuna B. Tarim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A context-aware computing mediated dynamic service composition and reconfiguration for ubiquitous environment. - Tao Gong; Zheng Hu 001; Haifeng Liu; Feng Lin; Dian Zhou; Hui Tian 003 (IOT, 2012)

Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks. - Huimin She; Zhonghai Lu; Axel Jantsch; Dian Zhou; Li-Rong Zheng 001 (Int. J. Distributed Sens. Networks, 2012)

An Efficient Method for Evaluating Analog Circuit Performance Bounds Under Process Variations. - Po-Yu Kuo; Siwat Saibua; Guanming Huang; Dian Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. - Zhaori Bi; Wei Li; Dian Zhou; Xuan Zeng 001; Sheng-Guo Wang (ASICON, 2013)

A practical method for auto-design and optimization of DC-DC buck converter. - Guanming Huang; Dian Zhou; Xuan Zeng 001; Shengguo Wang (ASICON, 2013)

FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp. - Minghua Li; Dian Zhou; Sheng-Guo Wang; Xuan Zeng 001 (ASICON, 2013)

Oscillator phase noise verification accounting for process variations. - Liuxi Qian; Dian Zhou; Xuan Zeng 001; Shengguo Wang (ASICON, 2013)

A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement. - Liuxi Qian; Dian Zhou; Xuan Zeng 001; Fan Yang 001; Shengguo Wang (ASICON, 2013)

Design automation of analog circuit considering the process variations. - Dian Zhou; Guanming Huang (ASICON, 2013)

An Adaptive Social Influence Propagation Model Based on Local Network Topology. - Haifeng Liu; Zheng Hu 001; Hui Tian 003; Dian Zhou (EC-Web, 2013)

Cumulative Probability Distribution Model for Evaluating User Behavior Prediction Algorithms. - Haifeng Liu; Zheng Hu 001; Dian Zhou; Hui Tian 003 (SocialCom, 2013)

An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells. - Guanming Huang; Liuxi Qian; Siwat Saibua; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues. - Wei Li; Dian Zhou; Minghua Li; Binh P. Nguyen; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. - Yunfeng Yang; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2015)

Analog circuit performance bound estimation based on extreme value theory. - Minghua Li; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (MWSCAS, 2015)

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. - Liuxi Qian; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation. - Chenjie Yang; Fan Yang 001; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2016)

Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. - Chenlei Fang; Qicheng Huang; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Xin Li 001 (DAC, 2016)

Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. - Qicheng Huang; Chenlei Fang; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Xin Li 001 (DAC, 2016)

Efficient spatial variation modeling via robust dictionary learning. - Changhai Liao; Jun Tao 001; Xuan Zeng 001; Yangfeng Su; Dian Zhou; Xin Li 001 (DATE, 2016)

Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. - Bo Peng; Fan Yang 001; Changhao Yan; Xuan Zeng 001; Dian Zhou (DATE, 2016)

Efficient Memory Partitioning for Parallel Data Access via Data Reuse. - Jincheng Su; Fan Yang 001; Xuan Zeng 001; Dian Zhou (FPGA, 2016)

Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation. - Handi Yu; Jun Tao 001; Changhai Liao; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (ICCAD, 2016)

Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit. - Zhelun Yu; Jincheng Su; Fan Yang 001; Yangfeng Su; Xuan Zeng 001; Dian Zhou; Weiping Shi (ISCAS, 2016)

High-speed link verification based on statistical inference. - Xuan Zeng 001; Chenlei Fang; Qicheng Huang; Fan Yang 001; Dian Zhou; Wei Cai 003; Weiping Shi (ISCAS, 2016)

PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor. - Minghua Li; Guancheng Chen; Qijun Wang; Yonghua Lin; H. Peter Hofstee; Per Stenström; Dian Zhou (IEEE Comput. Archit. Lett., 2016)

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. - Minghua Li; Guanming Huang; Xiulong Wu; Liuxi Qian; Xuan Zeng 001; Dian Zhou (Sci. China Inf. Sci., 2016)

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. - Changhai Liao; Jun Tao 001; Handi Yu; Zhangwen Tang; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree. - Changhai Liao; Jun Tao 001; Xuan Zeng 001; Yangfeng Su; Dian Zhou; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. - Yunfeng Yang; Wai-Shing Luk; David Z. Pan; Hai Zhou 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

An efficient algorithm for stencil planning and optimization in E-beam lithography. - Jiabei Ge; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2017)

Network flow based cut redistribution and insertion for advanced 1D layout design. - Ye Zhang 011; Wai-Shing Luk; Fan Yang 001; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2017)

Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. - Wenlong Lv; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2017)

An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid. - Chao Yan; Hengliang Zhu; Dian Zhou; Xuan Zeng 001 (DATE, 2017)

Efficient SVM-based hotspot detection using spectral clustering. - Fan Yang 001; Charles C. Chiang; Xuan Zeng 001; Dian Zhou (ISCAS, 2017)

A grid-based detailed routing algorithm for advanced 1D process. - Ye Zhang 011; Fan Yang 001; Dian Zhou; Xuan Zeng 001; Xiangdong Hu (ISCAS, 2017)

Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis. - Shuhan Zhang; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Shun Li; Xiangdong Hu (ISCAS, 2017)

A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. - Kun Lu; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ISPA/IUCC, 2017)

Study on mechanical properties of radial permanent magnet bearing. - Dian Zhou; Gang Zhang (CIS/RAM, 2017)

Hear the heart: Daily cardiac health monitoring using Ear-ECG and machine learning. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (UEMCON, 2017)

PulsePrint: Single-arm-ECG biometric human identification using deep learning. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (UEMCON, 2017)

A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG. - Qingxue Zhang; Xuan Zeng 001; Wenchuang Walter Hu; Dian Zhou (IEEE Access, 2017)

HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (IEEE Access, 2017)

An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer. - Guanming Huang; Donesh Gillin; Dian Zhou; Jin Liu 004; Xuan Zeng 001; Po-Yu Kuo (Sci. China Inf. Sci., 2017)

A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Biomed. Eng., 2017)

Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse. - Jincheng Su; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Jie Chen 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification. - Fan Yang 001; Subarna Sinha; Charles C. Chiang; Xuan Zeng 001; Dian Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations. - Wei Zeng; Hengliang Zhu; Xuan Zeng 001; Dian Zhou; Ruey-Wen Liu; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. - Zhaori Bi; Dian Zhou; Sheng-Guo Wang; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. - Yunfeng Yang; Wai-Shing Luk; Hai Zhou 001; David Z. Pan; Dian Zhou; Changhao Yan; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. - Mengshuo Wang; Changhao Yan; Xin Li 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Multi-objective bayesian optimization for analog/RF circuit synthesis. - Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DAC, 2018)

A general graph based pessimism reduction framework for design optimization of timing closure. - Fulin Peng; Changhao Yan; Chunyang Feng; Jianquan Zheng; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2018)

An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits. - Jinyuan Zhai; Changhao Yan; Sheng-Guo Wang; Dian Zhou (DAC, 2018)

An efficient data reuse strategy for multi-pattern data access. - Wensong Li; Fan Yang 001; Hengliang Zhu; Xuan Zeng 001; Dian Zhou (ICCAD, 2018)

Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design. - Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ICML, 2018)

A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (Biomed. Signal Process. Control., 2018)

Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. - Mengshuo Wang; Wenlong Lv; Fan Yang 001; Changhao Yan; Wei Cai 003; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. - Yishi Yang; Hengliang Zhu; Zhaori Bi; Changhao Yan; Dian Zhou; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. - Hengliang Zhu; Feng Hu; Hao Zhou 008; David Z. Pan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits. - Wenlong Lyu; Pan Xue; Fan Yang 001; Changhao Yan; Zhiliang Hong; Xuan Zeng 001; Dian Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. - Jinyuan Zhai; Changhao Yan; Sheng-Guo Wang; Dian Zhou; Hai Zhou 001; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2018)

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. - Ye Zhang 011; Wenlong Lyu; Wai-Shing Luk; Fan Yang 001; Hai Zhou 001; Dian Zhou; David Z. Pan; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. - Hao Zhou 008; Hengliang Zhu; Tao Cui; David Z. Pan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Parallel Global Placement on CPU via Parallel Reduction. - Huaidong Gao; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ASICON, 2019)

Learning Sparse Patterns in Deep Neural Networks. - Weijing Wen; Fan Yang 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ASICON, 2019)

Efficient Layout Hotspot Detection via Binarized Residual Neural Network. - Yiyang Jiang; Fan Yang 001; Hengliang Zhu; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (DAC, 2019)

An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. - Shuhan Zhang; Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001; Xiangdong Hu (DAC, 2019)

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. - Xin Wei; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (DATE, 2019)

Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. - Shuhan Zhang; Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2019)

VSkLCG A Method for Cross-Platform Vulnerability Search in Firmware. - Mushuai Han; Dongdong Zhao 001; Hong Lin 004; Dian Zhou; Jianwen Xiang; Zhongjin Liu; Yanzhen Xing (DSA, 2019)

Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network. - Zhengqi Gao; Jun Tao 001; Fan Yang 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ICCAD, 2019)

Vulnerability Detection in Firmware Based on Clonal Selection Algorithm. - Man Yu; Dongdong Zhao 001; Dian Zhou; Linjun Ran; Jianwen Xiang; Zhongjin Liu; Yanzhen Xing (SSCI, 2019)

Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. - Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse. - Wensong Li; Fan Yang 001; Hengliang Zhu; Xuan Zeng 001; Dian Zhou (ACM Trans. Reconfigurable Technol. Syst., 2019)

An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. - Xiang Ge; Fan Yang 001; Hengliang Zhu; Xuan Zeng 001; Dian Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. - Shuhan Zhang; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2020)

An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. - Xiaodong Wang; Tianchen Gu; Changhao Yan; Xiulong Wu; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2020)

An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. - Shuhan Zhang; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (DAC, 2020)

An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. - Biao He; Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2020)

VSFBS: Vulnerability Search in Firmware Based on String. - Zhibin Zhang; Dian Zhou; Jiqing Rao; Dongdong Zhao 001; Wenhua Hu; Jianwen Xiang; Zhongjin Liu; Yanzhen Xing (DSA, 2020)

An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. - Binbin Liu; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis. - Jialin Lu; Shuhan Zhang; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior. - Jiahe Shi; Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

Learning Low-Rank Structured Sparsity in Recurrent Neural Networks. - Weijing Wen; Fan Yang 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

Application of Deep Learning Algorithm in Feature Mining and Rapid Identification of Colorectal Image. - Mingchao Du; Min Tao; Jian Hong; Dian Zhou; Shuihua Wang (IEEE Access, 2020)

Projection based Active Gaussian Process Regression for Pareto Front Modeling. - Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (CoRR, 2020)

Nonlinear CNN: improving CNNs with quadratic convolutions. - Yiyang Jiang; Fan Yang 001; Hengliang Zhu; Dian Zhou; Xuan Zeng 001 (Neural Comput. Appl., 2020)

Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference. - Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution. - Zhengqi Gao; Jun Tao 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation. - Fulin Peng; Handi Yu; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Analog/RF Post-silicon Tuning via Bayesian Optimization. - Renjian Pan; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (ACM Trans. Design Autom. Electr. Syst., 2020)

A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits. - Jiahui Hu; Changhao Yan; Chao Guo; Ronggui Jiang; Dian Zhou; Xuan Zeng 001 (ASICON, 2021)

High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure. - Yan Wang; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASICON, 2021)

Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits. - Zhengqi Gao; Zihao Chen; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2021)

A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. - Jiangli Huang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2021)

NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. - Junzhe Cai; Changhao Yan; Yuzhe Ma; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (DAC, 2021)

An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. - Yue Shen; Changhao Yan; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DATE, 2021)

Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. - Jiangli Huang; Shuhan Zhang; Cong Tao; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ISCAS, 2021)

IEEE Access Special Section Editorial: Advanced Information Sensing and Learning Technologies for Data-Centric Smart Health Applications. - Qingxue Zhang; Vincenzo Piuri; Edward A. Clancy; Dian Zhou; Thomas Penzel; Wenchuang Walter Hu (IEEE Access, 2021)

IEEE Access Special Section Editorial: Smart Health Sensing and Computational Intelligence: From Big Data to Big Impacts. - Qingxue Zhang; Vincenzo Piuri; Edward A. Clancy; Dian Zhou; Thomas Penzel; Wenchuang Walter Hu; Hui Zheng (IEEE Access, 2021)

Deep learning of nanopore sensing signals using a bi-path network. - Dario Dematties; Chenyu Wen; Mauricio David Pérez; Dian Zhou; Shi-Li Zhang (CoRR, 2021)

An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. - Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (CoRR, 2021)

Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. - Yiyang Jiang; Fan Yang 001; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. - Jingyao Zhao; Changhao Yan; Zhaori Bi; Fan Yang 001; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2022)

An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. - Xiaodong Wang; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (DAC, 2022)

A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. - Longlong Yang; Cuiyang Ding; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ICCAD, 2022)

A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. - Xu Fu; Changhao Yan; Zhaori Bi; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2022)

LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. - Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (MLCAD, 2022)

Predicting the quality of answers with less bias in online health question answering communities. - Yan Qiu; Shuai Ding 001; Di Tian; Caiyun Zhang; Dian Zhou (Inf. Process. Manag., 2022)

Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space. - Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. - Jun Tao 001; Handi Yu; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. - Xiaodong Wang; Changhao Yan; Yuzhe Ma; Bei Yu 001; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. - Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. - Yifan Wang; Zhaori Bi; Yuxue Xie; Tao Wu; Xuan Zeng 001; Shuang Chen; Dian Zhou (IEEE J. Biomed. Health Informatics, 2022)

Efficient Layout Hotspot Detection via Neural Architecture Search. - Yiyang Jiang; Fan Yang 001; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. - Aidong Zhao; Xianan Wang; Zixiao Lin; Zhaori Bi; Xudong Li; Changhao Yan; Fan Yang 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2023)

Machine Learning Electrocardiogram for Mobile Cardiac Pattern Extraction. - Qingxue Zhang; Dian Zhou (Sensors, 2023)

Identification and Evolution of Soil Organic Carbon Density Caused by Coastal Rapid Siltation Based on Imaging Spectroscopy. - Aosheng Wang; Guanghui Zheng; Danping Wei; Caixia Jiao; Xianli Xie; Rong Zeng; Chengyi Zhao; Giri Kattel; Ying Xiong; Dian Zhou (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2023)

An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. - Jiangli Huang; Chuyu Wang; Yuyang Yan; Cong Tao; Fan Yang 001; Changhao Yan; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. - Biao He; Shuhan Zhang; Yifan Wang; Tianning Gao; Fan Yang 001; Changhao Yan; Dian Zhou; Zhaori Bi; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Quantitative Analysis of Tidal Creek Evolution and Vegetation Variation in Silting Muddy Flats on the Yellow Sea. - Guanghui Zheng; Yan Wang; Chengyi Zhao; Wen Dai; Giri Raj Kattel; Dian Zhou (Remote. Sens., 2023)

A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). - Ruiyu Lyu; Yuan Meng; Aidong Zhao; Zhaori Bi; Keren Zhu 001; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. - Xuyang Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Ye Lu 005; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. - Zihao Chen; Jiangli Huang; Yiting Liu; Fan Yang 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing. - Tianchen Gu; Ruiyu Lyu; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Tao Cui; Xin Liu 001; Zaikun Zhang; Xuan Zeng 001 (DAC, 2024)

EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. - Handa Sun; Zhaori Bi; Wenning Jiang; Ye Lu 005; Changhao Yan; Fan Yang 001; Wenchuang Hu; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

Efficient ILT via Multigrid-Schwartz Method. - Shuyuan Sun; Fan Yang 001; Bei Yu 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. - Yuan Meng; Ruiyu Lyu; Zhaori Bi; Changhao Yan; Fan Yang 001; Wenchuang Hu; Dian Zhou; Xuan Zeng 001 (DATE, 2024)

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. - Ruiyu Lyu; Aidong Zhao; Yuan Meng; Keren Zhu 001; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ICCAD, 2024)

Exploring High-dimensional Search Space via Voronoi Graph Traversing. - Aidong Zhao; Xuyang Zhao; Tianchen Gu; Zhaori Bi; Xinwei Sun 001; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (UAI, 2024)

Music conditioned 2D hand gesture dance generation with HGS. - Dian Zhou; Shiguang Liu; Qing Xu 002 (Comput. Animat. Virtual Worlds, 2024)

pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. - Zhaoting Chen; Junzhe Cai; Changhao Yan; Zhaori Bi; Yuzhe Ma; Bei Yu 001; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. - Tianchen Gu; Wangzhen Li; Aidong Zhao; Zhaori Bi; Xudong Li; Fan Yang 001; Changhao Yan; Wenchuang Walter Hu; Dian Zhou; Tao Cui; Xin Liu 001; Zaikun Zhang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. - Aidong Zhao; Tianchen Gu; Zhaori Bi; Fan Yang 001; Changhao Yan; Xuan Zeng 001; Zixiao Lin; Wenchuang Walter Hu; Dian Zhou (ACM Trans. Design Autom. Electr. Syst., 2024)

ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Aidong Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

The Reasoning-Memorization Interplay in Language Models Is Mediated by a Single Direction. - Yihuai Hong; Meng Cao; Dian Zhou; Lei Yu; Zhijing Jin 001 (ACL (Findings), 2025)

INTO-OA: Interpretable Topology Optimization for Operational Amplifiers. - Jinyi Shen; Fan Yang 001; Li Shang; Zhaori Bi; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2025)

An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. - Tianning Gao; Yifan Wang; Ming Zhu 016; Xiulong Wu; Dian Zhou; Zhaori Bi (IEEE Trans. Very Large Scale Integr. Syst., 2025)

ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers. - Jinyi Shen; Fan Yang 001; Li Shang; Changhao Yan; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis. - Aidong Zhao; Ruiyu Lyu; Xuyang Zhao; Zhaori Bi; Fan Yang 001; Changhao Yan; Dian Zhou; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions. - Zhixuan Dong; Longlong Yang; Cuiyang Ding; Changhao Yan; Zhaori Bi; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Zheng Wu; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)