Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. - Dong Xiang; Krishnendu Chakrabarty; Dianwei Hu; Hideo Fujiwara (ATS, 2007)

Pattern-directed circuit virtual partitioning for test power reduction. - Qiang Xu 001; Dianwei Hu; Dong Xiang (ITC, 2007)

Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture. - Dong Xiang; Dianwei Hu; Qiang Xu 001; Alex Orailoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)