Multiple data access via a common cavity bus in circuit QED. - Dibyendu Chatterjee; Arijit Roy 001 (Int. J. Circuit Theory Appl., 2017)

An Improved 1T-DRAM Cell Using TiO2as the Source and Drain of an n-Channel PD-SOI MOSFET. - Dibyendu Chatterjee; Anil Kottantharayil (DRC, 2018)

Body Bias Impact on ION Degradation in SiGe-Channel pMOS without Si-Cap for DRAM Periphery. - Dibyendu Chatterjee; Uma Sharma; Hiroshi Murai; Tomohiko Kudo; Raghu Singanamalla; Haitao Liu (IRPS, 2024)