Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies. - Sabyasachi Sengupta; Somavalli Ramanathan; Biswadeep Chatterjee; Dibyendu Goswami (VLSI Design, 2001)

Reducing Library Development Cycle Time through an Optimum Layout Create Flow. - Rituparna Mandal; Dibyendu Goswami; Arup Dash (ASP-DAC/VLSI Design, 2002)