An Integrated Highly Parallel Architecture for Image Reconstruction. - Didier Lattard; Guy Mazaré (Advances in Computer Graphics Hardware, 1988)

An Integrated Asynchronous Cellular Array to Do Parallel Image Reconstruction. - Didier Lattard; Guy Mazaré (MVA, 1988)

Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction). - Didier Lattard (1989)

Massively parallel architecture: application to neural net emulation and image reconstruction. - Didier Lattard; Bernard Faure; Guy Mazaré (ASAP, 1990)

A VLSI implementation of parallel image reconstruction. - Didier Lattard; Guy Mazaré (CVGIP Graph. Model. Image Process., 1991)

A Data Dependent Architecture Based on Seeded Region Growing Strategy for Advanced Morphological Operators. - Dominique Noguet; Alain Merle; Didier Lattard (ISMM, 1996)

Proposition of a benchmark for evaluation of cores mapping onto NoC architectures. - Julien Delorme; Dominique Houzet; Romain Lemaire; Didier Lattard (ReCoSoC, 2005)

Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. - Romain Lemaire; Fabien Clermidy; Yves Durand; Didier Lattard; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2005)

Trends in complex SoC Design: From technology variability to multiprocessor architectures. - Didier Lattard (ICECS, 2007)

A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. - Didier Lattard; Edith Beigné; Christian Bernard; Catherine Bour; Fabien Clermidy; Yves Durand; Jean Durupt; Didier Varreau; Pascal Vivet; Pierre Penard; Arnaud Bouttier; Friedbert Berens (ISSCC, 2007)

An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications. - Carolynn Bernier; Frédéric Hameau; Gérard Billiot; Emeric de Foucauld; Stéphanie Robinet; Didier Lattard; Jean Durupt; Francois Dehmas; Laurent Ouvry; Pierre Vincent (ESSCIRC, 2008)

A flexible modeling and simulation framework for Design Space Exploration. - Camille Jalier; Didier Lattard; Gilles Sassatelli (SoC, 2008)

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. - Didier Lattard; Edith Beigné; Fabien Clermidy; Yves Durand; Romain Lemaire; Pascal Vivet; Friedbert Berens (IEEE J. Solid State Circuits, 2008)

High level modelling and performance evaluation of address mapping in NAND flash memory. - Walid Lafi; Didier Lattard; Ahmed Amine Jerraya (ICECS, 2009)

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. - Camille Jalier; Didier Lattard; Ahmed Amine Jerraya; Gilles Sassatelli; Pascal Benoit; Lionel Torres (DATE, 2010)

Flexible and distributed real-time control on a 4G telecom MPSoC. - Camille Jalier; Didier Lattard; Gilles Sassatelli; Pascal Benoit; Lionel Torres (ISCAS, 2010)

A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio. - Camille Jalier; Didier Lattard; Gilles Sassatelli; Pascal Benoit; Lionel Torres (ISVLSI, 2010)

An efficient hierarchical router for large 3D NoCs. - Walid Lafi; Didier Lattard; Ahmed Amine Jerraya (International Symposium on Rapid System Prototyping, 2010)

A 3D reconfigurable platform for 4G telecom applications. - Walid Lafi; Didier Lattard; Ahmed Amine Jerraya (DATE, 2011)

Algorithm architecture co-design for ultra low-power image sensor. - Timothé Laforest; Antoine Dupret; Arnaud Verdant; Didier Lattard; Patrick Villard (Sensors, Cameras, and Systems for Industrial and Scientific Applications, 2012)

A Stackable LTE Chip for Cost-effective 3D Systems. - Walid Lafi; Didier Lattard; Ahmed Amine Jerraya (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip. - Walid Lafi; Didier Lattard; Ahmed Amine Jerraya (Softw. Pract. Exp., 2012)

Non-coherent detection of M-ary orthogonal signals using Compressive Sensing. - Vincent Lenoir; Didier Lattard; Francois Dehmas; Dominique Morche; Ahmed Amine Jerraya (CSNDSP, 2014)

Computational load reduction by downsampling for energy-efficient digital baseband. - Vincent Lenoir; Didier Lattard; Francois Dehmas; Dominique Morche; Ahmed Amine Jerraya (NEWCAS, 2014)

3D advanced integration technology for heterogeneous systems. - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (3DIC, 2015)

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. - Edith Beigné; Fabien Clermidy; Didier Lattard; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet (ISCAS, 2015)

An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs. - Vincent Lenoir; Didier Lattard; Ahmed Amine Jerraya (ISCAS, 2015)

Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB. - Vincent Lenoir; Warody Lombardi; Didier Lattard; Ahmed Amine Jerraya (NEWCAS, 2015)

ITAC: A complete 3D integration test platform. - Didier Lattard; Lucile Arnaud; Arnaud Garnier; Nicolas Bresson; Franck Bana; R. Segaud; Amadine Jouve; H. Jacquinot; Stéphane Moreau; Karim Azizi-Mourier; C. Chantre; Pascal Vivet; et al. (3DIC, 2016)

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (ISSCC, 2016)

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. - Perceval Coudrain; Papa Momar Souare; Rafael Prieto; Vincent Fiori; Alexis Farcy; Laurent Le Pailleur; Jean-Philippe Colonna; Cristiano Santos; Pascal Vivet; M. Haykel Ben Jamaa; Denis Dutoit; François de Crecy; et al. (IEEE Des. Test, 2016)

Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. - Imed Jani; Didier Lattard; Pascal Vivet; Edith Beigné (NEWCAS, 2017)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. - Imed Jani; Didier Lattard; Pascal Vivet; Lucile Arnaud; Edith Beigné (ETS, 2018)

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. - Pascal Vivet; Sébastien Thuries; Olivier Billoint; Sylvain Choisnet; Didier Lattard; Edith Beigné; Perrine Batude (ICECS, 2018)

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. - François Andrieu; Perrine Batude; Laurent Brunet; Claire Fenouillet-Béranger; Didier Lattard; Sébastien Thuries; Olivier Billoint; Richard Fournel; Maud Vinet (ICICDT, 2018)

Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability. - Lucile Arnaud; Stéphane Moreau; Amadine Jouve; Imed Jani; Didier Lattard; F. Fournel; C. Euvrard; Y. Exbrayat; Viorel Balan; Nicolas Bresson; S. Lhostis; J. Jourdon; et al. (IRPS, 2018)

Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. - Olivier Billoint; Karim Azizi-Mourier; Gerald Cibrario; Didier Lattard; Mehdi Mouhdach; Sébastien Thuries; Pascal Vivet (3DIC, 2019)

Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. - Imed Jani; Didier Lattard; Pascal Vivet; Lucile Arnaud; Edith Beigné (3DIC, 2019)

Advanced 3D Technologies and Architectures for 3D Smart Image Sensors. - Pascal Vivet; Gilles Sicard; Laurent Millet; Stéphane Chevobbe; Karim Ben Chehida; Luis Angel Cubero; Monte Alegre; Maxence Bouvier; Alexandre Valentian; Maria Lepecq; Thomas Dombek; Olivier Bichler; et al. (DATE, 2019)

Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. - Imed Jani; Didier Lattard; Pascal Vivet; Jean Durupt; Sébastien Thuries; Edith Beigné (ETS, 2019)

M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. - Sébastien Thuries; Olivier Billoint; Sylvain Choisnet; Romain Lemaire; Pascal Vivet; Perrine Batude; Didier Lattard (DATE, 2020)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. - Mona Ezzadeen; D. Bosch; Bastien Giraud; Sylvain Barraud; Jean-Philippe Noël; Didier Lattard; Joris Lacord; Jean-Michel Portal; François Andrieu (CoRR, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. - J. Luge-Alvarez; J. B. David; Alexandre Siligaris; Vincent Puyal; G. Moritz; Tadeu Mota Frutuoso; V. Lapras; Claire Fenouillet-Béranger; Laurent Brunet; P. Vincent; Didier Lattard; Xavier Garros; et al. (VLSI Technology and Circuits, 2024)