Floating-gate EEPROM cell: threshold voltage sensibility to geometry. - Jean-Michel Portal; L. Forli; Didier Née (ISCAS (1), 2002)

Floating-gate EEPROM cell model based on MOS model 9. - Jean-Michel Portal; L. Forli; Didier Née (ISCAS (3), 2002)

An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. - Jean-Michel Portal; L. Forli; Hassen Aziza; Didier Née (ITC, 2002)

An Automated Design Methodology for EEPROM Cell (ADE). - Jean-Michel Portal; L. Forli; Hassen Aziza; Didier Née (MTDT, 2002)

Infrastructure IP for Back-End Yield Improvement. - L. Forli; Jean-Michel Portal; Didier Née; Bertrand Borot (ITC, 2003)

EEPROM Memory: Threshold Voltage Built In Self Diagnosis. - Jean-Michel Portal; Hassen Aziza; Didier Née (ITC, 2003)

A New Embedded Measurement Structure for eDRAM Capacitor. - Laurent Lopez; Jean-Michel Portal; Didier Née (DATE, 2005)

Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. - B. Saillet; Jean-Michel Portal; Didier Née (DFT, 2005)

EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. - Jean-Michel Portal; Hassen Aziza; Didier Née (J. Electron. Test., 2005)

Back-end soft and hard defect monitoring using a single test chip. - Fabrice Rigaud; Jean-Michel Portal; Hassen Aziza; Didier Née; Julien Vast; Fabrice Argoud; Bertrand Borot (Microelectron. Reliab., 2011)