Application of system semantics to VLSI for the transformational design of a parameterized booth multiplier module - a case study. - Luc Claesen; R. T. Boute; J. De Man; W. Ploegaerts; M. Seutter; J. Vanslembrouck; Diederik Verkest (Microprocessing and Microprogramming, 1989)

Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language. - W. Ploegaerts; Diederik Verkest; Luc Claesen; Hugo De Man (Microprocessing and Microprogramming, 1989)

Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. - Diederik Verkest; Luc J. M. Claesen; Hugo De Man (EURO-DAC, 1990)

Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis. - Catia M. Angelo; Diederik Verkest; Luc J. M. Claesen; Hugo De Man (TPHOLs, 1991)

A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU. - Diederik Verkest; Luc J. M. Claesen; Hugo De Man (Designing Correct Circuits, 1992)

A Description Methodology for Parameterized Modules in the Boyer-Moore Logic. - Diederik Verkest; J. Vandenbergh; Luc J. M. Claesen; Hugo De Man (TPCD, 1992)

On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification. - Catia M. Angelo; Diederik Verkest; Luc J. M. Claesen; Hugo De Man (Formal Methods Syst. Des., 1993)

A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU. - Diederik Verkest; Luc J. M. Claesen; Hugo De Man (Formal Methods Syst. Des., 1994)

CoWare - a design environment for heterogenous hardware/software systems. - Karl van Rompaey; Ivo Bolsens; Hugo De Man; Diederik Verkest (EURO-DAC, 1996)

CoWare - A design environment for heterogeneous hardware/software systems. - Diederik Verkest; Karl van Rompaey; Ivo Bolsens; Hugo De Man (Des. Autom. Embed. Syst., 1996)

Derivation of Formal Representations from Process-Based Specification and Implementation Models. - Steven Vercauteren; Diederik Verkest; Gjalt G. de Jong; Bill Lin 001 (ISSS, 1997)

Hardware/software co-design of digital telecommunication systems. - Ivo Bolsens; Hugo J. De Man; Bill Lin 001; Karl van Rompaey; Steven Vercauteren; Diederik Verkest (Proc. IEEE, 1997)

Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. - Julio Leao da Silva Jr.; Chantal Ykman-Couvreur; Miguel Miranda; Kris Croes; Sven Wuytack; Gjalt G. de Jong; Francky Catthoor; Diederik Verkest; Paul Six; Hugo De Man (DAC, 1998)

Efficient Verification using Generalized Partial Order Analysis. - Steven Vercauteren; Diederik Verkest; Gjalt G. de Jong; Bill Lin 001 (DATE, 1998)

Power exploration for dynamic data types through virtual memory management refinement. - Julio Leao da Silva Jr.; Francky Catthoor; Diederik Verkest; Hugo De Man (ISLPED, 1998)

Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications. - Francky Catthoor; Diederik Verkest; Erik Brockmeyer (ISSS, 1998)

Timed executable system specification of an ADSL modem using a C++ based design environment: a case study. - Dirk Desmet; Michiel Esvelt; Prabhat Avasare; Diederik Verkest; Hugo De Man (CODES, 1999)

Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback. - Arnout Vandecappelle; Miguel Miranda; Erik Brockmeyer; Francky Catthoor; Diederik Verkest (DAC, 1999)

Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints. - Steven Vercauteren; Jan van der Steen; Diederik Verkest (DATE, 1999)

Hardware-software co-design of embedded systems using CoWare's N2C methodology for application development. - S. K. Tsasakou; Nikos S. Voros; M. V. Koziotis; Diederik Verkest; Aggeliki S. Prayati; Alexios N. Birbas (ICECS, 1999)

Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications. - Chantal Ykman-Couvreur; Jurgen Lambrecht; Diederik Verkest; Francky Catthoor; Hugo De Man (ISSS, 1999)

Guest Editorial. - Gaetano Borriello; Diederik Verkest; Francky Catthoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management. - Diederik Verkest; Julio Leao da Silva Jr.; Chantal Ykman-Couvreur; Kris Croes; Miguel Miranda; Sven Wuytack; Francky Catthoor; Gjalt G. de Jong; Hugo De Man (J. VLSI Signal Process., 1999)

Dynamic scheduling of concurrent tasks with cost performance trade-off. - Peng Yang; Dirk Desmet; Francky Catthoor; Diederik Verkest (CASES, 2000)

Extended design reuse trade-offs in hardware-software architecture mapping. - Frederik Vermeulen; Francky Catthoor; Diederik Verkest; Hugo De Man (CODES, 2000)

Operating system based software generation for systems-on-chip. - Dirk Desmet; Diederik Verkest; Hugo De Man (DAC, 2000)

System Level Design Using C++. - Diederik Verkest; Joachim Kunkel; Frank Schirrmeister (DATE, 2000)

Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications. - Frederik Vermeulen; Francky Catthoor; Hugo De Man; Diederik Verkest (DATE, 2000)

Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player. - Aggeliki S. Prayati; Chun Wong; Paul Marchal; Nathalie Cossement; Francky Catthoor; Rudy Lauwereins; Diederik Verkest; Hugo De Man; Alexios N. Birbas (ICPP Workshops, 2000)

Flexible hardware acceleration for multimedia oriented microprocessors. - Frederik Vermeulen; Lode Nachtergaele; Francky Catthoor; Diederik Verkest; Hugo De Man (MICRO, 2000)

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform. - Paul Marchal; Chun Wong; Aggeliki S. Prayati; Nathalie Cossement; Francky Catthoor; Rudy Lauwereins; Diederik Verkest; Hugo De Man (PACS, 2000)

Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications. - Frederik Vermeulen; Francky Catthoor; Diederik Verkest; Hugo De Man (IEEE Trans. Very Large Scale Integr. Syst., 2000)

C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN. - Diederik Verkest; Wolfgang Eberle; Patrick Schaumont; Bert Gyselinckx; Serge Vemalde (CICC, 2001)

Task concurrency management methodology summary. - Chun Wong; Paul Marchal; Peng Yang; Francky Catthoor; Hugo De Man; Aggeliki S. Prayati; Nathalie Cossement; Rudy Lauwereins; Diederik Verkest (DATE, 2001)

Optimisation Problems for Dynamic Concurrent Task-Based Systems. - Diederik Verkest; Peng Yang; Chun Wong; Paul Marchal (ICCAD, 2001)

System-level interconnect architecture exploration for custom memory organizations. - Tycho van Meeuwen; Arnout Vandecappelle; Allert van Zelst; Francky Catthoor; Diederik Verkest (ISSS, 2001)

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications. - Miguel Miranda; C. Ghez; Chidamber Kulkarni; Francky Catthoor; Diederik Verkest (ISSS, 2001)

Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs. - Peng Yang; Chun Wong; Paul Marchal; Francky Catthoor; Dirk Desmet; Diederik Verkest; Rudy Lauwereins (IEEE Des. Test Comput., 2001)

System-level performance optimization of the data queueing memory management in high-speed network processors. - Chantal Ykman-Couvreur; Jurgen Lambrecht; Diederik Verkest; Francky Catthoor; Aristides Nikologiannis; George E. Konstantoulakis (DAC, 2002)

Design Technology for Networked Reconfigurable FPGA Platforms. - Steve Guccione; Diederik Verkest; Ivo Bolsens (DATE, 2002)

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. - Yajun Ha; Radovan Hipik; Serge Vernalde; Diederik Verkest; Marc Engels; Rudy Lauwereins; Hugo De Man (FPL, 2002)

Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. - Théodore Marescaux; T. Andrei Bartic; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (FPL, 2002)

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (FPT, 2002)

Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera. - Dirk Desmet; Prabhat Avasare; Paul Coene; Stijn Decneut; Filip Hendrickx; Théodore Marescaux; Jean-Yves Mignolet; Robert Pasko; Patrick Schaumont; Diederik Verkest (Embedded Processor Design Challenges, 2002)

Dynamic memory management methodology applied to embedded telecom network systems. - Chantal Ykman-Couvreur; Jurgen Lambrecht; Diederik Verkest; Francky Catthoor; Bengt Svantesson; Ahmed Hemani; F. Wolf (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (DATE, 2003)

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. - Jean-Yves Mignolet; Vincent Nollet; Paul Coene; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (DATE, 2003)

Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems. - Vincent Nollet; Jean-Yves Mignolet; T. Andrei Bartic; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (Engineering of Reconfigurable Systems and Algorithms, 2003)

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (ESTIMedia, 2003)

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (FCCM, 2003)

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. - Théodore Marescaux; Jean-Yves Mignolet; T. Andrei Bartic; W. Moffat; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (FPL, 2003)

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (FPL, 2003)

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. - Javier Resano; Daniel Mozos; Diederik Verkest; Serge Vernalde; Francky Catthoor (FPL, 2003)

Designing an Operating System for a Heterogeneous Reconfigurable So. - Vincent Nollet; Paul Coene; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (IPDPS, 2003)

Highly scalable network on chip for reconfigurable systems. - T. Andrei Bartic; Jean-Yves Mignolet; Vincent Nollet; Théodore Marescaux; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (SoC, 2003)

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. - Richard Stahl; Robert Pasko; Luc Rijnders; Diederik Verkest; Serge Vernalde; Rudy Lauwereins; Francky Catthoor (SCOPES, 2003)

Hardware Architectures for the Efficient Implementation of Multi-Service Broadband Access and Multimedia Home Networks. - Theofanis Orphanoudakis; Stylianos Perissakis; Kostas Pramataris; Nikos A. Nikolaou; Nicholas Zervos; Matthias Steck; Christoph Baumhof; Diederik Verkest; Chantal Ykman-Couvreur; Gregory Doumenis; Fotis Karoubalis; Ioanna Theologitou; et al. (Telecommun. Syst., 2003)

Power-efficient flexible processor architecture for embedded applications. - Frederik Vermeulen; Francky Catthoor; Lode Nachtergaele; Diederik Verkest; Hugo De Man (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Operating-system controlled network on chip. - Vincent Nollet; Théodore Marescaux; Diederik Verkest; Jean-Yves Mignolet; Serge Vernalde (DAC, 2004)

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Rudy Lauwereins (DATE, 2004)

Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model. - Richard Stahl; Francky Catthoor; Rudy Lauwereins; Diederik Verkest (Euro-Par, 2004)

Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. - T. Andrei Bartic; Dirk Desmet; Jean-Yves Mignolet; Théodore Marescaux; Diederik Verkest; Serge Vernalde; Rudy Lauwereins; J. Miller; Frédéric Robert (FPL, 2004)

High-Level Data-Access Analysis for Characterisation of (Sub)task-Level Parallelism in Java. - Richard Stahl; Robert Pasko; Francky Catthoor; Rudy Lauwereins; Diederik Verkest (HIPS, 2004)

Design Style Case Study for Embedded Multi Media Compute Nodes. - Andy Lambrechts; Tom Vander Aa; Murali Jayapala; Guillermo Talavera; Anthony Leroy; Adelina Shickova; Francisco Barat; Bingfeng Mei; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; et al. (RTSS, 2004)

Run-time support for heterogeneous multitasking on reconfigurable SoCs. - Théodore Marescaux; Vincent Nollet; Jean-Yves Mignolet; T. Andrei Bartic; W. Moffat; Prabhat Avasare; Paul Coene; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (Integr., 2004)

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (Microprocess. Microsystems, 2004)

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. - Andy Lambrechts; Praveen Raghavan; Anthony Leroy; Guillermo Talavera; Tom Vander Aa; Murali Jayapala; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; Frédéric Robert; Jordi Carrabina (ASAP, 2005)

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs. - Anthony Leroy; Paul Marchal; Adelina Shickova; Francky Catthoor; Frédéric Robert; Diederik Verkest (CODES+ISSS, 2005)

Low Cost Task Migration Initiation in a Heterogeneous MP-SoC. - Vincent Nollet; Prabhat Avasare; Jean-Yves Mignolet; Diederik Verkest (DATE, 2005)

Centralized end-to-end flow control in a best-effort network-on-chip. - Prabhat Avasare; Vincent Nollet; Jean-Yves Mignolet; Diederik Verkest; Henk Corporaal (EMSOFT, 2005)

Object-Distribution Analysis: Technique for Parallel Loop Distribution of Object-Oriented Programs. - Richard Stahl; Francky Catthoor; Diederik Verkest (ICPP Workshops, 2005)

Object-Distribution Analysis for Program Decomposition and Re-Clustering. - Richard Stahl; Francky Catthoor; Diederik Verkest (IPDPS, 2005)

Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform. - Bert Geelen; Gauthier Lafruit; Vissarion Ferentinos; Rudy Lauwereins; Diederik Verkest (PATMOS, 2005)

Architecture Exploration for a Reconfigurable Architecture Template. - Bingfeng Mei; Andy Lambrechts; Diederik Verkest; Jean-Yves Mignolet; Rudy Lauwereins (IEEE Des. Test Comput., 2005)

A Reconfiguration Manager for Dynamically Reconfigurable Hardware. - Javier Resano; Daniel Mozos; Diederik Verkest; Francky Catthoor (IEEE Des. Test Comput., 2005)

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (DATE, 2006)

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment. - Vincent Nollet; Prabhat Avasare; Diederik Verkest; Henk Corporaal (ERSA, 2006)

Compiler-Driven Leakage Energy Reduction in Banked Register Files. - David Atienza; Praveen Raghavan; José L. Ayala; Giovanni De Micheli; Francky Catthoor; Diederik Verkest; Marisa López-Vallejo (PATMOS, 2006)

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. - Daniele Paolo Scarpazza; Praveen Raghavan; David Novo; Francky Catthoor; Diederik Verkest (PATMOS, 2006)

Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications. - Bert Geelen; Aris Ferentinos; Francky Catthoor; Arnout Vandecappelle; Gauthier Lafruit; Thanos Stouraitis; Rudy Lauwereins; Diederik Verkest (SiPS, 2006)

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. - Praveen Raghavan; Satyakiran Munaga; Estela Rey Ramos; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (ARCS, 2007)

Very wide register: an asymmetric register file organization for low power embedded processors. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest; Henk Corporaal (DATE, 2007)

Adaptive mapping to resource availability for dynamic wavelet-based applications. - Vissarion Ferentinos; Bert Geelen; Francky Catthoor; Gauthier Lafruit; Thanos Stouraitis; Rudy Lauwereins; Diederik Verkest (ESTIMedia, 2007)

A Quick Safari Through the MPSoC Run-Time Management Jungle. - Vincent Nollet; Diederik Verkest; Henk Corporaal (ESTIMedia, 2007)

Semi Custom Design: A Case Study on SIMD Shufflers. - Praveen Raghavan; Nandhavel Sethubalasubramanian; Satyakiran Munaga; Estela Rey Ramos; Murali Jayapala; Oliver Weiss; Francky Catthoor; Diederik Verkest (PATMOS, 2007)

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations. - Kristof Denolf; Marco Jan Gerrit Bekooij; Johan Cockx; Diederik Verkest; Henk Corporaal (EURASIP J. Adv. Signal Process., 2007)

A Systematic Approach to Design Low-Power Video Codec Cores. - Kristof Denolf; Adrian Chirila-Rus; Paul R. Schumacher; Robert D. Turney; Kees A. Vissers; Diederik Verkest; Henk Corporaal (EURASIP J. Embed. Syst., 2007)

Energy-aware compilation and hardware design for VLIW embedded systems. - José L. Ayala; Marisa López-Vallejo; David Atienza; Praveen Raghavan; Francky Catthoor; Diederik Verkest (Int. J. Embed. Syst., 2007)

Coffee: COmpiler Framework for Energy-Aware Exploration. - Praveen Raghavan; Andy Lambrechts; Javed Absar; Murali Jayapala; Francky Catthoor; Diederik Verkest (HiPEAC, 2008)

Spatial locality trade-offs of wavelet-based applications in dynamic execution environments. - Bert Geelen; Aris Ferentinos; Francky Catthoor; Gauthier Lafruit; Diederik Verkest (ICASSP, 2008)

Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. - Mladen Berekovic; Frank Bouwens; Tom Vander Aa; Diederik Verkest (PATMOS, 2008)

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. - Andy Lambrechts; Praveen Raghavan; Murali Jayapala; Francky Catthoor; Diederik Verkest (VLSI Design, 2008)

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. - David Atienza; Praveen Raghavan; José Luis Ayala; Giovanni De Micheli; Francky Catthoor; Diederik Verkest; Marisa López-Vallejo (Integr., 2008)

A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing. - Bruno Bougard; Bjorn De Sutter; Diederik Verkest; Liesbet Van der Perre; Rudy Lauwereins (IEEE Micro, 2008)

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip. - Anthony Leroy; Dragomir Milojevic; Diederik Verkest; Frédéric Robert; Francky Catthoor (IEEE Trans. Computers, 2008)

Run-Time Management of a MPSoC Containing FPGA Fabric Tiles. - Vincent Nollet; Prabhat Avasare; Hendrik Eeckhaut; Diederik Verkest; Henk Corporaal (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Multimedia systems in a changing technology landscape. - Diederik Verkest (ESTIMedia, 2009)

EMPIRE: Empirical power/area/timing models for register files. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (Microprocess. Microsystems, 2009)

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. - Paul Marchal; Bruno Bougard; Guruprasad Katti; Michele Stucchi; Wim Dehaene; Antonis Papanikolaou; Diederik Verkest; Bart Swinnen; Eric Beyne (Proc. IEEE, 2009)

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (IEEE Trans. Computers, 2009)

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts. - Bert Geelen; Vissarion Ferentinos; Francky Catthoor; Gauthier Lafruit; Diederik Verkest; Rudy Lauwereins; Thanos Stouraitis (ACM Trans. Design Autom. Electr. Syst., 2009)

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. - Andy Lambrechts; Praveen Raghavan; Murali Jayapala; Bingfeng Mei; Francky Catthoor; Diederik Verkest (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments. - Bert Geelen; Vissarion Ferentinos; Francky Catthoor; Spyridon Toulatos; Gauthier Lafruit; Thanos Stouraitis; Rudy Lauwereins; Diederik Verkest (J. Signal Process. Syst., 2009)

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications. - Dragomir Milojevic; Luc J. M. Montperrus; Diederik Verkest (J. Signal Process. Syst., 2009)

Design and Tool Flow of Multimedia MPSoC Platforms. - Bjorn De Sutter; Diederik Verkest; Erik Brockmeyer; Eric Delfosse; Arnout Vandecappelle; Jean-Yves Mignolet (J. Signal Process. Syst., 2009)

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM. - Pavel Poliakov; Ankur Anchlia; Marie Garcia Bardon; Bram Rooseleer; Bart De Wachter; Nadine Collaert; Koen van der Zanden; Wim Dehaene; Diederik Verkest; Miguel Corbalan Miranda (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements. - Bert Geelen; Vissarion Ferentinos; Francky Catthoor; Gauthier Lafruit; Diederik Verkest; Rudy Lauwereins; Thanos Stouraitis (ACM Trans. Embed. Comput. Syst., 2010)

A Safari Through the MPSoC Run-Time Management Jungle. - Vincent Nollet; Diederik Verkest; Henk Corporaal (J. Signal Process. Syst., 2010)

Analysis of microbump induced stress effects in 3D stacked IC technologies. - Andrej Ivankovic; Geert Van der Plas; V. Moroz; M. Choi; Vladimir Cherman; Abdelkarim Mercha; Paul Marchal; Marcel Gonzalez; Geert Eneman; Wenqi Zhang; Thibault Buisson; Mikael Detalle; et al. (3DIC, 2011)

Real-time high-definition stereo matching on FPGA. - Lu Zhang 018; Ke Zhang 012; Tian Sheuan Chang; Gauthier Lafruit; Georgi Krasimirov Kuzmanov; Diederik Verkest (FPGA, 2011)

Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories. - Pavel Poliakov; Pieter Blomme; Alessandro Vaglio Pret; Miguel Corbalan Miranda; Roel Gronheid; Diederik Verkest; Jan Van Houdt; Wim Dehaene (Microelectron. Reliab., 2012)

Design issues in heterogeneous 3D/2.5D integration. - Dragomir Milojevic; Pol Marchal; Erik Jan Marinissen; Geert Van der Plas; Diederik Verkest; Eric Beyne (ASP-DAC, 2013)

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (DAC, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

System-level assessment and area evaluation of Spin Wave logic circuits. - Odysseas Zografos; Praveen Raghavan; Luca Gaetano Amarù; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Diederik Verkest; Aaron Thean (NANOARCH, 2014)

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. - Bertrand Parvais; Piet Wambacq; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; Ken Sawada; Kazuki Nomoto; Tetsuya Oishi; Hiroaki Ammo (A-SSCC, 2015)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Characterization and simulation methodology for time-dependent variability in advanced technologies. - Pieter Weckx; Ben Kaczer; Praveen Raghavan; Jacopo Franco; Marko Simicic; Philippe J. Roussel; Dimitri Linten; Aaron Thean; Diederik Verkest; Francky Catthoor; Guido Groeseneken (CICC, 2015)

Impact of interconnect multiple-patterning variability on SRAMs. - Ioannis Karageorgos; Michele Stucchi; Praveen Raghavan; Julien Ryckaert; Zsolt Tokei; Diederik Verkest; Rogier Baert; Sushil Sakhare; Wim Dehaene (DATE, 2015)

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (ICICDT, 2015)

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. - Marie Garcia Bardon; P. Schuddinck; Praveen Raghavan; Doyoung Jang; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Impact of device and interconnect process variability on clock distribution. - Nathalie Fievet; Praveen Raghavan; Rogier Baert; Frédéric Robert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Impact of fin shape variability on device performance towards 10nm node. - Kazuyuki Tomida; Keizo Hiraga; Morin Dehan; Geert Hellings; Doyoung Jang; Kenichi Miyaguchi; Thomas Chiarella; Minsoo Kim; Anda Mocuta; Naoto Horiguchi; Abdelkarim Mercha; Diederik Verkest; et al. (ICICDT, 2015)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance. - Raf Appeltans; Stefan Cosemans; Praveen Raghavan; Diederik Verkest; Liesbet Van der Perre; Wim Dehaene (NVMSA, 2015)

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. - Bon Woong Ku; Peter Debacker; Dragomir Milojevic; Praveen Raghavan; Diederik Verkest; Aaron Thean; Sung Kyu Lim (ISLPED, 2016)

5nm: Has the time for a device change come? - Praveen Raghavan; Marie Garcia Bardon; Peter Debacker; P. Schuddinck; Doyoung Jang; Rogier Baert; Diederik Verkest; Aaron Voon-Yew Thean (ISQED, 2016)

SRAM designs for 5nm node and beyond: Opportunities and challenges. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Alessio Spessot; Diederik Verkest; Anda Mocuta (ICICDT, 2017)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Scaling CMOS beyond Si FinFET: an analog/RF perspective. - Bertrand Parvais; Geert Hellings; Marko Simicic; Pieter Weckx; Jérôme Mitard; Doyoung Jang; V. Deshpande; B. van Liempc; Anabela Veloso; A. Vandooren; Niamh Waldron; Piet Wambacq; et al. (ESSDERC, 2018)

Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications. - Jonas Doevenspeck; Robin Degraeve; Andrea Fantini; Peter Debacker; Diederik Verkest; Rudy Lauwereins; Wim Dehaene (IRPS, 2019)

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. - Bram-Ernst Verhoef; Nathan Laubeuf; Stefan Cosemans; Peter Debacker; Ioannis A. Papistas; Arindam Mallik; Diederik Verkest (CoRR, 2019)

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. - Ioannis A. Papistas; Stefan Cosemans; Bram Rooseleer; Jonas Doevenspeck; Myung Hee Na; Arindam Mallik; Peter Debacker; Diederik Verkest (CICC, 2021)

Noise tolerant ternary weight deep neural networks for analog in-memory inference. - Jonas Doevenspeck; Peter Vrancx; Nathan Laubeuf; Arindam Mallik; Peter Debacker; Diederik Verkest; Rudy Lauwereins; Wim Dehaene (IJCNN, 2021)

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. - Debjyoti Bhattacharjee; Nathan Laubeuf; Stefan Cosemans; Ioannis A. Papistas; Arindam Mallik; Peter Debacker; Myung Hee Na; Diederik Verkest (ISCAS, 2021)

Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. - Michele Caselli; Ioannis A. Papistas; Stefan Cosemans; Arindam Mallik; Peter Debacker; Diederik Verkest (NEWCAS, 2021)

Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. - Michele Caselli; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest (ISCAS, 2022)

Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing. - Michele Caselli; Subhali Subhechha; Peter Debacker; Arindam Mallik; Diederik Verkest (ISCAS, 2022)

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. - Kodai Ueyoshi; Ioannis A. Papistas; Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Man Shi; Qilin Zheng; Juan Sebastian Piedrahita Giraldo; Peter Vrancx; Jonas Doevenspeck; Debjyoti Bhattacharjee; Stefan Cosemans; et al. (ISSCC, 2022)

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. - Simei Yang; Debjyoti Bhattacharjee; Vinay B. Y. Kumar; Saikat Chatterjee; Sayandip De; Peter Debacker; Diederik Verkest; Arindam Mallik; Francky Catthoor (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. - Nathan Laubeuf; Jonas Doevenspeck; Ioannis A. Papistas; Michele Caselli; Stefan Cosemans; Peter Vrancx; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Francky Catthoor; Rudy Lauwereins (ACM Trans. Design Autom. Electr. Syst., 2022)

Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. - Subhali Subhechha; Stefan Cosemans; Attilio Belmonte; Nouredine Rassoul; Shamin Houshmand Sharifi; Peter Debacker; Diederik Verkest; Romain Delhougne; Gouri Sankar Kar (IMW, 2023)

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. - Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Kodai Ueyoshi; Ioannis A. Papistas; Man Shi; Qilin Zheng; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Marian Verhelst (IEEE J. Solid State Circuits, 2023)