Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver. - Deniz Dosluoglu; Kun-Da Chu; Diego Peña-Colaiocco; Ivan Zhao; Visvesh Sathe 001; Jacques C. Rudell (ESSCIRC, 2022)

Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. - Chi-Hsiang Huang 001; Arindam Mandal; Diego Peña-Colaiocco; Edevaldo Pereira Da Silva; Visvesh S. Sathe 001 (ISSCC, 2022)

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. - Diego Peña-Colaiocco; Chi-Hsiang Huang 001; Kun-Da Chu; Jacques Christophe Rudell; Visvesh S. Sathe 001 (ISSCC, 2022)

Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. - Chi-Hsiang Huang 001; Arindam Mandal; Diego Peña-Colaiocco; Edevaldo Pereira Da Silva; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2023)