A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis. - Dieison Antonello Deprá; Vagner Santos Da Rosa; Sergio Bampi (SBCCI, 2008)

A method for HW functional verification through HW/SW co-simulation in complex systems: H.264/AVC decoder as case study. - Dieison Antonello Deprá; Bruno Zatt; Sergio Bampi (LATW, 2009)

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis. - Dieison Antonello Deprá; Sergio Bampi (VLSI-SoC, 2009)