Custom circuit design as a driver of microprocessor performance. - David H. Allen; Sang H. Dhong; H. Peter Hofstee; Jens Leenstra; Kevin J. Nowka; Daniel L. Stasiak; Dieter F. Wendel (IBM J. Res. Dev., 2000)

A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. - Jens Leenstra; Jürgen Pille; Antje Müller; Wolfram M. Sauer; Rolf Sautter; Dieter F. Wendel (IEEE J. Solid State Circuits, 2001)

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. - Dac C. Pham; Erwin Behnen; Mark Bolliger; H. Peter Hofstee; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; Yoshio Masubuchi; Stephen D. Posluszny; Mack W. Riley; et al. (CICC, 2005)

Cell Processor Low-Power Design Methodology. - Daniel L. Stasiak; Rajat Chaudhry; Dennis Cox; Stephen D. Posluszny; James D. Warnock; Steve Weitzel; Dieter F. Wendel; Michael Wang 001 (IEEE Micro, 2005)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. - James D. Warnock; Dieter F. Wendel; Tony Aipperspach; Erwin Behnen; Robert A. Cordes; Sang H. Dhong; Koji Hirairi; Hiroaki Murakami; Shohji Onishi; Dac C. Pham; Jürgen Pille; Stephen D. Posluszny; et al. (IEEE J. Solid State Circuits, 2006)

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V. - Jürgen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (ISSCC, 2007)

Cell Broadband Engine processor: Design and implementation. - Mack W. Riley; James D. Warnock; Dieter F. Wendel (IBM J. Res. Dev., 2007)

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. - Juergen Pille; Chad Adams; Todd Christensen; Scott R. Cottier; Sebastian Ehrenreich; Fumihiro Kono; Daniel Nelson; Osamu Takahashi; Shunsako Tokito; Otto A. Torreiter; Otto Wagner; Dieter F. Wendel (IEEE J. Solid State Circuits, 2008)

A 32nm 0.5V-supply dual-read 6T SRAM. - Jente B. Kuang; Jeremy D. Schaub; Fadi H. Gebara; Dieter F. Wendel; Sudesh Saroop; Tuyet Nguyen; Thomas Fröhnel; Antje Müller; Christopher M. Durham; Rolf Sautter; Bryan Lloyd; Bryan J. Robbins; et al. (CICC, 2010)

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. - Jürgen Pille; Dieter F. Wendel; Otto Wagner; Rolf Sautter; Wolfgang Penth; Thomas Fröhnel; Stefan Büttner; Otto A. Torreiter; Martin Eckert; Jose Paredes; David Hrusecky; David Ray; et al. (ISSCC, 2010)

POWER7TM local clocking and clocked storage elements. - James D. Warnock; Leon J. Sigal; Dieter F. Wendel; K. Paul Muller; Joshua Friedrich; Victor V. Zyuban; Ethan H. Cannon; A. J. KleinOsowski (ISSCC, 2010)

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. - Dieter F. Wendel; Ronald N. Kalla; Robert Cargnoni; Joachim G. Clabes; Joshua Friedrich; Roland Frech; James A. Kahle; Balaram Sinharoy; William J. Starke; Scott A. Taylor; Steve Weitzel; Sam G. Chu; et al. (ISSCC, 2010)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM. - Jente B. Kuang; Jeremy D. Schaub; Fadi H. Gebara; Dieter F. Wendel; Thomas Fröhnel; Sudesh Saroop; Sani R. Nassif; Kevin J. Nowka (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction. - Alexander Fritsch; Michael Kugel; Rolf Sautter; Dieter F. Wendel; Juergen Pille; Otto A. Torreiter; Shankar Kalyanasundaram; Daniel A. Dobson (ESSCIRC, 2015)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

IBM z13 circuit design and methodology. - James D. Warnock; Christopher J. Berry; Michael H. Wood; Leon J. Sigal; Yun-Chan Myung; Guenter Mayer; Mark D. Mayo; Y. Chan; Frank Malgioglio; Gerald Strevig; Charudhattan Nagarajan; Sean M. Carey; et al. (IBM J. Res. Dev., 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. - Philipp Salz; A. Frisch; Wolfgang Penth; J. Noack; T. Kalla; Rolf Sautter; Michael Kugel; Otto A. Torreiter; G. Sapp; Mike Lee; Eric Fluhr; A. Rozenfeld; et al. (ESSCIRC, 2017)