Architekturkonzepte für massiv-parallele, opto-elektronische Rechnersysteme. - Dietmar Fey; Konrad Zürl; A. Hetzner (ARCS, 1992)

Modellierung, Simulation und Bewertung paralleler digitaler optischer Systeme. - Dietmar Fey (1993)

Parallele digitale optische Recheneinheiten - Modellierung, Simulation und Bewertung. - Werner Erhard; Dietmar Fey (Teubner, 1994)

Transformation of a 2-D VLSI Systolic Adder Circuit in 3-D Circuits Using Optical Interconnections. - Dietmar Fey (Euro-Par, Vol. II, 1996)

Principles for Optoelectronic 3D Architectures and Correponding Algorithms to Calculate Standard Functions. - Bernd Kasche; Dietmar Fey (Parcella, 1996)

Massively Parallel Volume Rendering by Exploiting a 3d Optoelectronic Arithmetic Logical Unit. - Bernd Kasche; Dietmar Fey; T. Höhn; Werner Erhard (ARCS, 1999)

3D Optoelectronic Fix Point Unit and Its Advantages Processing 3D Data. - Bernd Kasche; Dietmar Fey; T. Höhn; Werner Erhard (Euro-Par, 1999)

Architekturen und Entwurfssysteme für ein optoelektronisches 3-D VLSI. - Dietmar Fey; Werner Erhard (Informationstechnik Tech. Inform., 1999)

Optical interconnects for neural and reconfigurable VLSI architectures. - Dietmar Fey; Werner Erhard; Matthies Gruber; Jürgen Jahns; Hartmut Bartelt; Guido Grimm; Lutz Hoppe; Stefan Sinzinger (Proc. IEEE, 2000)

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits. - Dietmar Fey; Marko Degenkolb (J. Supercomput., 2000)

A digital multi-layer-perceptron hardware architecture based on three dimensional massively parallel optoelectronic circuits. - Klaus D. Maier 001; Clemens Beckstein; Reinhard Blickhan; Dietmar Fey; Werner Erhard (Informatica (Slovenia), 2001)

Optik in der Rechentechnik - photonisches VLSI und optische Netzwerke. - Dietmar Fey (Teubner, 2002)

Optotechnologie in der IT. - Dietmar Fey (it Inf. Technol., 2003)

OptoRAP - eine rekonfigurierbare optoelektronische Parallelprozessor-Architektur für die Bildvorverarbeitung (OptoRAP - a Reconfigurable Optoelectronic Parallel Processor Architecture for Image Pre-Processing). - Dietmar Fey; Andreas Loos (it Inf. Technol., 2003)

Reconfigurable OPTO-ASICs as base for future self-organizing CMOS cameras. - Dietmar Fey; Daniel Schmidt 003; Andreas Loos (ARCS Workshops, 2004)

Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips. - Dietmar Fey; Lutz Hoppe; Andreas Loos (PARELEC, 2004)

A Framework for Optimising Parameter Studies on a Cluster Computer by the Example of Micro-system Design. - Dietmar Fey; Marcus Komann; Christian Kauhaus (PVM/MPI, 2004)

Marching Pixels: A new Organic Computing Prinicple for Smart CMOS Camera Chips. - Dietmar Fey; Daniel Schmidt 003 (ARCS Workshops, 2005)

Marching-pixels: a new organic computing paradigm for smart sensor processor arrays. - Dietmar Fey; Daniel Schmidt 003 (Conf. Computing Frontiers, 2005)

Calculation of Single-File Diffusion Using Grid-Enabled Parallel Generic Cellular Automata Simulation. - Marcus Komann; Christian Kauhaus; Dietmar Fey (PVM/MPI, 2005)

Parallelization of Simulations for Various Magnetic System Models on Small-Sized Cluster Computers with MPI. - Frank Schurz; Dietmar Fey; Dmitri Berkov (ICCSA (5), 2006)

SOGOS - A Distributed Meta Level Architecture for the Self-Organizing Grid of Services. - Clemens Beckstein; Peter Dittrich; Christian Erfurth; Dietmar Fey; Birgitta König-Ries; Martin Mundhenk; Harald Sack (MDM, 2006)

Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach. - Christian Kauhaus; Dietmar Fey (PARELEC, 2006)

Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware. - Marcus Komann; Dietmar Fey (PARELEC, 2006)

A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems. - Michael Schmidt 004; Andreas Loos; Dietmar Fey (PARELEC, 2006)

An Organic Computing architecture for visual microprocessors based on Marching Pixels. - Dietmar Fey; Marcus Komann; Frank Schurz; Andreas Loos (ISCAS, 2007)

Comparison of Evolving Uniform, Non-uniform Cellular Automaton, and Genetic Programming for Centroid Detection with Hardware Agents. - Marcus Komann; Andreas Mainka; Dietmar Fey (PaCT, 2007)

A Virtual Test Environment for MPI Development: Quick Answers to Many Small Questions. - Wolfgang Schnerring; Christian Kauhaus; Dietmar Fey (PVM/MPI, 2007)

Realising emergent image preprocessing tasks in cellular-automaton-alike massively parallel hardware. - Marcus Komann; Dietmar Fey (Int. J. Parallel Emergent Distributed Syst., 2007)

Solving the problem of enforced restriction to few states while evolving cellular automata. - Marcus Komann; Dietmar Fey (Automata, 2008)

Emergent algorithms for centroid and orientation detection in high-performance embedded cameras. - Marcus Komann; Alexander Kröller; Christiane Schmidt 001; Dietmar Fey; Sándor P. Fekete (Conf. Computing Frontiers, 2008)

Pollarder: An Architecture Concept for Self-adapting Parallel Applications in Computational Science. - Andreas Schäfer 006; Dietmar Fey (ICCS (1), 2008)

Challenges of MPI over IPv6. - Adrian Knoth; Christian Kauhaus; Dietmar Fey; Lars Schneidenbach; Bettina Schnor (ICNS, 2008)

A Profitability Heuristic that Reduces the Parameter Dependence of Dynamic Load Balancing. - Jakob Erdmann; Andreas Schäfer 006; Christian Kauhaus; Dietmar Fey (Informatiktage, 2008)

LibGeoDecomp: A Grid-Enabled Library for Geometric Decomposition Codes. - Andreas Schäfer 006; Dietmar Fey (PVM/MPI, 2008)

Distributed vision with smart pixels. - Sándor P. Fekete; Dietmar Fey; Marcus Komann; Alexander Kröller; Marc Reichenbach; Christiane Schmidt 001 (SCG, 2009)

On the Effectiveness of Evolution Compared to Time-Consuming Full Search of Optimal 6-State Automata. - Marcus Komann; Patrick Ediger; Dietmar Fey; Rolf Hoffmann (EuroGP, 2009)

Evaluating the evolvability of emergent agents with different numbers of states. - Marcus Komann; Dietmar Fey (GECCO, 2009)

Herausforderungen der Technischen Informatik beim Unkonventionellen Rechnen. - Dietmar Fey (GI Jahrestagung, 2009)

Model-Driven Design and Organic Computing – Two Different but Possibly Accordable Concepts for the Design of Embedded Systems. - Dietmar Fey (ISORC, 2009)

Dynamically Programmable Image Processor for Compact Vision Systems. - Andreas Loos; Michael Schmidt 004; Dietmar Fey; Jens Grobel (CIT, 2010)

Revising the Trade-off between the Number of Agents and Agent Intelligence. - Marcus Komann; Dietmar Fey (EvoApplications (1), 2010)

Marching Pixels - Rechnen mit Hardware-Agenten im 2D Pixelraum. - Dietmar Fey (GI Jahrestagung (2), 2010)

Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities. - Matthias Sand; Volkmar Sieh; Dietmar Fey (HPCS, 2010)

Framework for Distributed Evolutionary Algorithms in Computational Grids. - Steffen Limmer; Dietmar Fey (ISICA (1), 2010)

Realizing Real-Time Centroid Detection of Multiple Objects with Marching Pixels Algorithms. - Dietmar Fey; Marcus Komann; Marc Reichenbach; Ralf Seidler (ISORC Workshops, 2010)

Simulation and Optimized Design of High Density Optical Crossconnect Systems for Massively Parallel Computing Architectures. - Ulrich Lohmann; Jürgen Jahns; Steffen Limmer; Dietmar Fey (OSC, 2010)

An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels. - Michael Schmidt 004; Dietmar Fey (ReConFig, 2010)

Seamless high speed simulation of VHDL components in the context of comprehensive computing systems using the virtual machine faumachine. - Stefan Potyra; Matthias Sand; Volkmar Sieh; Dietmar Fey (WSC, 2010)

Unconventional Computing - Reversible Signed Digit Adders for Future Nanocomputing Devices (Unkonventionelles Rechnen - reversible Addierer für künftiges Nanocomputing). - Dietmar Fey; Steffen Limmer (it Inf. Technol., 2010)

Emergent Computing with Marching Pixels for Real-Time Smart Camera Applications. - Dietmar Fey; Marcus Komann (Organic Computing, 2011)

Generic Emergent Computing in Chip Architectures. - Marc Reichenbach; Ralf Seidler; Dietmar Fey; Benjamin Pfundt (Organic Computing, 2011)

Competence research: teaching embedded micro/nano systems. - Steffen Jaschke; Sigrid E. Schubert; André Schäfer; Rainer Brück 001; Bruno Kleinert; Harald Schmidt; Dietmar Fey (WESE, 2011)

Evolutionary optimization of layouts for high density free space optical network links. - Steffen Limmer; Dietmar Fey; Ulrich Lohmann; Jürgen Jahns (GECCO, 2011)

Analytical Model for the Optimization of Self-Organizing Image Processing Systems Utilizing Cellular Automata. - Marc Reichenbach; Michael Schmidt 004; Dietmar Fey (ISORC Workshops, 2011)

A normative competence structure model for embedded micro- and nanosystems development. - André Schäfer; Rainer Brück 001; Steffen Jaschke; Sigrid E. Schubert; Dietmar Fey; Bruno Kleinert; Harald Schmidt (ITiCSE, 2011)

Parallel simulation of dendritic growth on unstructured grids. - Andreas Schäfer 006; Julian Hammer; Dietmar Fey (IA3@SC, 2011)

High Performance Stencil Code Algorithms for GPGPUs. - Andreas Schäfer 006; Dietmar Fey (ICCS, 2011)

Performance comparison of designated preprocessing white light interferometry algorithms on emerging multi- and many-core architectures. - Max Schneider; Dietmar Fey; Daniel Kapusi; Torsten Machleidt (ICCS, 2011)

A Speed-Up Study for a Parallelized White Light Interferometry Preprocessing Algorithm on a Virtual Embedded Multiprocessor System. - Dominik Schoenwetter; Max Schneider; Dietmar Fey (ARCS Workshops, 2012)

Competence model for embedded micro-and nanosystems. - André Schäfer; Rainer Brück 001; Bruno Kleinert; Harald Schmidt; Dietmar Fey; Steffen Büchner 001; Steffen Jaschke; Sigrid E. Schubert (EDUCON, 2012)

Evolutionary Design of Active Free Space Optical Networks Based on Digital Mirror Devices. - Steffen Limmer; Dietmar Fey; Ulrich Lohmann; Jürgen Jahns (EvoApplications, 2012)

Optimization of a Short-Range Proximity Effect Correction Algorithm in E-Beam Lithography Using GPGPUs. - Max Schneider; Nikola Belic; Christoph Sambale; Ulrich Hofmann; Dietmar Fey (ICA3PP (1), 2012)

A Generic VHDL Template for 2D Stencil Code Applications on FPGAs. - Michael Schmidt 004; Marc Reichenbach; Dietmar Fey (ISORC Workshops, 2012)

The empirically refined competence structure model for embedded micro- and nanosystems. - André Schäfer; Rainer Brück 001; Steffen Büchner 001; Steffen Jaschke; Sigrid E. Schubert; Dietmar Fey; Bruno Kleinert; Harald Schmidt (ITiCSE, 2012)

Heterogeneous computer architectures: An image processing pipeline for optical metrology. - Marc Reichenbach; Ralf Seidler; Dietmar Fey (ReConFig, 2012)

Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAs. - Michael Schmidt 004; Dietmar Fey (ReConFig, 2012)

Zero-Overhead Interfaces for High-Performance Computing Libraries and Kernels. - Andreas Schäfer 006; Dietmar Fey (SC Companion, 2012)

A Predictive Performance Model for Stencil Codes on Multicore CPUs. - Andreas Schäfer 006; Dietmar Fey (VECPAR, 2012)

Realizing real-time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware. - Dietmar Fey; Marc Reichenbach; Marcus Komann; Ralf Seidler (Concurr. Comput. Pract. Exp., 2012)

Optical multiplexing techniques for photonic Clos networks in High Performance Computing Architectures. - Dietmar Fey; Max Schneider; Jürgen Jahns; Hans Knuppertz (J. Supercomput., 2012)

Smart sensor architectures for embedded biosignal analysis. - Benjamin Pfundt; Marc Reichenbach; Björn M. Eskofier; Dietmar Fey (DASIP, 2013)

An auto-tuning approach for optimizing base operators for non-destructive testing applications on heterogeneous multi-core architectures. - Thomas Heller; Dietmar Fey; Markus Rehak (ISORC, 2013)

Using HPX and LibGeoDecomp for scaling HPC applications on heterogeneous supercomputers. - Thomas Heller; Hartmut Kaiser; Andreas Schäfer 006; Dietmar Fey (ScalA@SC, 2013)

Performance investigations of genetic algorithms on graphics cards. - Johannes Hofmann 001; Steffen Limmer; Dietmar Fey (Swarm Evol. Comput., 2013)

On the Way to Big Data Applications in Industrial Computed Tomography. - Alexander Ditter; Dietmar Fey; Tobias Schön; Steven Oeckl (BigData Congress, 2014)

Performance Investigation and Tuning in the Interoperable Cloud4E Platform. - Steffen Limmer; Maik Srba; Dietmar Fey (Euro-Par Workshops (2), 2014)

Designing and manufacturing of real embedded multi-core CPUs: A holistic teaching approach in computer architecture. - Marc Reichenbach; Benjamin Pfundt; Dietmar Fey (EWME, 2014)

A Generic Approach for Analysis of White-Light Interferometry Data via User-Defined Algorithms. - Max Schneider; Dietmar Fey; Kay Wenzel; Torsten Machleidt (ICCSA (4), 2014)

HPX: A Task Based Programming Model in a Global Address Space. - Hartmut Kaiser; Thomas Heller; Bryce Adelstein-Lelbach; Adrian Serio; Dietmar Fey (PGAS, 2014)

A Portable Petascale Framework for Efficient Particle Methods with Custom Interactions. - Andreas Schäfer 006; Thomas Heller; Dietmar Fey (EuroMPI/ASIA, 2014)

Fast and generic hardware architecture for stereo block matching applications on embedded systems. - Konrad Häublein; Marc Reichenbach; Dietmar Fey (ReConFig, 2014)

Fast image processing for optical metrology utilizing heterogeneous computer architectures. - Marc Reichenbach; Ralf Seidler; Benjamin Pfundt; Dietmar Fey (Comput. Electr. Eng., 2014)

Services for numerical simulations and optimisations in grids. - Steffen Limmer; André Schneider; Christian Boehme; Dietmar Fey; Simon Schmitz; Achim Graupner; Martin Sülzle (Int. J. Parallel Emergent Distributed Syst., 2014)

Real-time correlation for locating systems utilizing heterogeneous computing architectures. - Marc Reichenbach; Maximilian Kasparek; Mohammad Alawieh; Konrad Häublein; Dietmar Fey (DASIP, 2015)

Architecture and simulation of a hybrid memristive multiplier network using redundant number representation. - Dietmar Fey; Jonathan Martschinke (IJCNN, 2015)

Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing. - Christian Herglotz; Jürgen Seiler; André Kaup; Arne Hendricks; Marc Reichenbach; Dietmar Fey (IPDPS Workshops, 2015)

Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors. - Johannes Hofmann 001; Dietmar Fey; Michael Riedmann; Jan Eitzinger; Georg Hager; Gerhard Wellein (PPAM (1), 2015)

FAUPU - A design framework for the development of programmable image processing architectures. - Marc Reichenbach; Tobias Lieske; Steffen Vaas; Konrad Häublein; Dietmar Fey (ReConFig, 2015)

Framework for parameter analysis of FPGA-based image processing architectures. - Marc Reichenbach; Benjamin Pfundt; Dietmar Fey (SAMOS, 2015)

Higher-level parallelization for local and distributed asynchronous task-based programming. - Hartmut Kaiser; Thomas Heller; Daniel Bourgeois; Dietmar Fey (ESPM@SC, 2015)

Tsunami and Storm Surge Simulation Using Low Power Architectures - Concept and Evaluation. - Dominik Schoenwetter; Alexander Ditter; Bruno Kleinert; Arne Hendricks; Vadym Aizinger; Harald Köstler; Dietmar Fey (SIMULTECH, 2015)

Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures. - Dominik Schoenwetter; Alexander Ditter; Bruno Kleinert; Arne Hendricks; Vadym Aizinger; Dietmar Fey (SIMULTECH (Selected Papers), 2015)

Hardware-software co-simulation for medical x-ray control units. - Bruno Kleinert; Gholam Reza Rahimi; Marc Reichenbach; Dietmar Fey (SimuTools, 2015)

FREACSIM: a framework for creating and simulating real-time capable network on chip systems and applications. - Dominik Schoenwetter; Ronald Veldema; Dietmar Fey (SimuTools, 2015)

SmartEco: An Integrated Solution from Load Balancing between the Grid and Consumers to Local Energy Efficiency. - Alexander Ditter; Dietmar Fey; Johannes Burner; Jörg Franke (UCC, 2015)

Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). - Frank Hannig; Dietmar Fey; Anton Lokhmotov (CoRR, 2015)

A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures. - Christian Hartmann 003; Anna Yupatova; Marc Reichenbach; Dietmar Fey; Reinhard German (CoRR, 2015)

Execution-Cache-Memory Performance Model: Introduction and Validation. - Johannes Hofmann 001; Jan Eitzinger; Dietmar Fey (CoRR, 2015)

Performance analysis of the Kahan-enhanced scalar product on current multicore processors. - Johannes Hofmann 001; Dietmar Fey; Jan Eitzinger; Georg Hager; Gerhard Wellein (CoRR, 2015)

Automatic Optimization of Hardware Accelerators for Image Processing. - Oliver Reiche; Konrad Häublein; Marc Reichenbach; Frank Hannig; Jürgen Teich; Dietmar Fey (CoRR, 2015)

OpenCL 2.0 for FPGAs using OCLAcc. - Franz Richter-Gottfried; Alexander Ditter; Dietmar Fey (CoRR, 2015)

Synthesis and optimization of image processing accelerators using domain knowledge. - Oliver Reiche; Konrad Häublein; Marc Reichenbach; Moritz Schmid; Frank Hannig; Jürgen Teich; Dietmar Fey (J. Syst. Archit., 2015)

Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. - Konrad Häublein; Christian Hartmann 003; Marc Reichenbach; Dietmar Fey (ARC, 2016)

Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks. - Johannes Hofmann 001; Dietmar Fey; Jan Eitzinger; Georg Hager; Gerhard Wellein (ARCS, 2016)

Investigation of strategies for an increasing population size in multi-objective CMA-ES. - Steffen Limmer; Dietmar Fey (CEC, 2016)

Teaching heterogeneous computer architectures using smart camera systems. - Benjamin Pfundt; Marc Reichenbach; Christian Hartmann 003; Konrad Häublein; Dietmar Fey (EWME, 2016)

Evaluating Performance and Energy-Efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures. - Arne Hendricks; Thomas Heller; Andreas Schäfer 006; Maximilian Kasparek; Dietmar Fey (ICCS, 2016)

An Application-Specific Instruction Set Processor for Power Quality Monitoring. - Steffen Vaas; Marc Reichenbach; Dietmar Fey (IPDPS Workshops, 2016)

C++ Classes and Templates for OpenCL Kernels with PATOS. - Franz Richter-Gottfried; Patrick Kreutzer; Alexander Ditter; Max Schneider; Dietmar Fey (IWOCL, 2016)

Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. - Dietmar Fey; Marc Reichenbach; Christopher Söll; Mehrdad Biglari; Jürgen Röber; Robert Weigel (MEMSYS, 2016)

Dataflow optimization for programmable embedded image preprocessing accelerators. - Tobias Lieske; Marc Reichenbach; Burkhard Ringlein; Dietmar Fey (ReConFig, 2016)

The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. - Steffen Vaas; Marc Reichenbach; Ulrich Margull; Dietmar Fey (ReConFig, 2016)

Hybrid code description for developing fast and resource efficient image processing architectures. - Konrad Häublein; Marc Reichenbach; Oliver Reiche; M. Akif Ozkan; Dietmar Fey; Frank Hannig; Jürgen Teich (SAMOS, 2016)

The AllScale Runtime Interface - Theoretical Foundation and Concept. - Arne Hendricks; Thomas Heller; Herbert Jordan; Peter Thoman; Thomas Fahringer; Dietmar Fey (MTAGS@SC, 2016)

An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors. - Johannes Hofmann 001; Dietmar Fey (E2SC@SC, 2016)

Improving instruction accurate simulation for parallel automotive applications. - Dominik Schoenwetter; Alexander Ditter; Dietmar Fey; Ralph Mader (SIES, 2016)

Hardware-software Co-simulation of Self-organizing Smart Home Networks - Who am I and Where Are the Others?. - Bruno Kleinert; Franziska Schäfer; Jupiter Bakakeu; Simone Weiß; Dietmar Fey (SIMULTECH, 2016)

Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware. - Dominik Schoenwetter; Alexander Ditter; Vadym Aizinger; Balthasar Reuter; Dietmar Fey (SIMULTECH, 2016)

Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU. - Bruno Kleinert; Simone Weiß; Franziska Schäfer; Jupiter Bakakeu; Dietmar Fey (SimuTools, 2016)

Closing the Performance Gap with Modern C++. - Thomas Heller; Hartmut Kaiser; Patrick Diehl; Dietmar Fey; Marc Alexander Schweitzer (ISC Workshops, 2016)

Performance analysis of the Kahan-enhanced scalar product on current multi- and manycore processors. - Johannes Hofmann 001; Dietmar Fey; Michael Riedmann; Jan Eitzinger; Georg Hager; Gerhard Wellein (CoRR, 2016)

Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics. - Tobias Lieske; Wilfried Uhring; Norbert Dumas; Jérémie Léonard; Dietmar Fey (DASIP, 2017)

LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. - Marc Reichenbach; Philipp Holzinger; Konrad Häublein; Tobias Lieske; Paul Blinzer; Dietmar Fey (DASIP, 2017)

The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs. - Steffen Vaas; Peter Ulbrich; Marc Reichenbach; Dietmar Fey (DASIP, 2017)

Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure. - Alexander Ditter; Gabriel Graf; Dietmar Fey (CCB@EuroSys, 2017)

Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. - Mehrdad Biglari; Dietmar Fey (MEMSYS, 2017)

Prototyping memristors in digital system with an FPGA-based testing environment. - Daniel Wust; Mehrdad Biglari; Johannes Knödtel; Marc Reichenbach; Christopher Söll; Dietmar Fey (PATMOS, 2017)

System on chip generation for multi-sensor and sensor fusion applications. - Tobias Lieske; Benjamin Pfundt; Steffen Vaas; Marc Reichenbach; Dietmar Fey (SAMOS, 2017)

An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. - Johannes Hofmann 001; Georg Hager; Gerhard Wellein; Dietmar Fey (ISC, 2017)

Memristive devices for computing: Beyond CMOS and beyond von Neumann. - Hoang Anh Du Nguyen; Jintao Yu; Lei Xie 005; Mottaqiallah Taouil; Said Hamdioui; Dietmar Fey (VLSI-SoC, 2017)

Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. - Johannes Hofmann 001; Dietmar Fey; Michael Riedmann; Jan Eitzinger; Georg Hager; Gerhard Wellein (Concurr. Comput. Pract. Exp., 2017)

Comparison of common parallel architectures for the execution of the island model and the global parallelization of evolutionary algorithms. - Steffen Limmer; Dietmar Fey (Concurr. Comput. Pract. Exp., 2017)

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach. - Dietmar Fey (CoRR, 2017)

Comprehensive curriculum for reconfigurable heterogeneous computer architecture education. - Benjamin Pfundt; Marc Reichenbach; Dietmar Fey (IET Circuits Devices Syst., 2017)

Introduction to the special issue on architecture of computing systems. - Frank Hannig; João M. P. Cardoso; Dietmar Fey (J. Syst. Archit., 2017)

Fast heterogeneous computing architectures for smart antennas. - Marc Reichenbach; Maximilian Kasparek; Konrad Häublein; Jan Niklas Bauer; Mohammad Alawieh; Dietmar Fey (J. Syst. Archit., 2017)

A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. - Sebastian Rachuj; Christian Herglotz; Marc Reichenbach; André Kaup; Dietmar Fey (ARCS, 2018)

The AllScale Runtime Application Model. - Herbert Jordan; Thomas Heller; Philipp Gschwandtner; Peter Zangerl; Peter Thoman; Dietmar Fey; Thomas Fahringer (CLUSTER, 2018)

Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures. - Marc Reichenbach; Lukas Liebischer; Steffen Vaas; Dietmar Fey (DASIP, 2018)

Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems. - Wolfgang Bauer; Philipp Holzinger; Marc Reichenbach; Steffen Vaas; Paul Hartke; Dietmar Fey (Euro-Par Workshops, 2018)

Autonomous Driving in the Curriculum of Computer Architecture. - Sebastian Rachuj; Marc Reichenbach; Steffen Vaas; Dietmar Fey (EWME, 2018)

The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM. - Anderson M. Maliszewski; Dalvan Griebler; Claudio Schepke; Alexander Ditter; Dietmar Fey; Luiz Gustavo Fernandes (HPCS, 2018)

Multi-level memristive voltage divider: programming scheme trade-offs. - Tobias Lieske; Mehrdad Biglari; Dietmar Fey (MEMSYS, 2018)

High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. - Mehrdad Biglari; Tobias Lieske; Dietmar Fey (NANOARCH, 2018)

A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. - Johannes Knödtel; Wolffhardt Schwabe; Tobias Lieske; Marc Reichenbach; Dietmar Fey (PATMOS, 2018)

A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems. - Philipp Holzinger; Marc Reichenbach; Dietmar Fey (SAMOS, 2018)

On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors. - Johannes Hofmann 001; Georg Hager; Dietmar Fey (ISC, 2018)

Case study on memristor-based multilevel memories. - Christopher Soell; Marc Reichenbach; Juergen Roeber; Amelie Hagelauer; Robert Weigel; Dietmar Fey (Int. J. Circuit Theory Appl., 2018)

Special issue on heterogeneous real-time image processing. - Dietmar Fey; Frank Hannig (J. Real Time Image Process., 2018)

An extended analysis of memory hierarchies for efficient implementations of image processing applications. - Christian Hartmann 003; Dietmar Fey (J. Real Time Image Process., 2018)

IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures. - Christian Hartmann 003; Konrad Häublein; Marc Reichenbach; Dietmar Fey (J. Real Time Image Process., 2018)

A programmable ternary CPU using hybrid CMOS/memristor circuits. - Daniel Wust; Dietmar Fey; Johannes Knödtel (Int. J. Parallel Emergent Distributed Syst., 2018)

Guest Editorial Memristive-Device-Based Computing. - Said Hamdioui; Pierre-Emmanuel Gaillardon; Dietmar Fey; Tajana Simunic Rosing (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Dataset for "The AllScale Runtime Application Model" publication. - Herbert Jordan; Thomas Heller; Philipp Gschwandtner; Peter Zangerl; Peter Thoman; Dietmar Fey; Thomas Fahringer (Zenodo, 2018)

A Generic Functional Simulation of Heterogeneous Systems. - Sebastian Rachuj; Marc Reichenbach; Dietmar Fey (ARCS, 2019)

System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration. - Burkhard Ringlein; François Abel; Alexander Ditter; Beat Weiss; Christoph Hagleitner; Dietmar Fey (FPL, 2019)

Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools. - Markus Fritscher; Johannes Knödtel; Marc Reichenbach; Dietmar Fey (ICECS, 2019)

A Hardware Inference Accelerator for Temporal Convolutional Networks. - Rashid Ali; Maen Mallah; Martin Leyh; Philipp Holzinger; Marco Breiling; Marc Reichenbach; Dietmar Fey (NORCAS, 2019)

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. - John Reuben; Dietmar Fey (NORCAS, 2019)

Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing. - Alexander Ditter; Michael Tielemann; Dietmar Fey (FAS*W@SASO/ICAC, 2019)

Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. - Tobias Lieske; Wilfried Uhring; Norbert Dumas; Anastasia Ioanna Skilitski; Jérémie Léonard; Dietmar Fey (J. Signal Process. Syst., 2019)

Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms. - Marc Reichenbach; Philipp Holzinger; Konrad Häublein; Tobias Lieske; Paul Blinzer; Dietmar Fey (J. Signal Process. Syst., 2019)

Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. - Steffen Vaas; Peter Ulbrich; Marc Reichenbach; Dietmar Fey (J. Signal Process. Syst., 2019)

TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities. - Shima Hosseinzadeh; Mehrdad Biglari; Dietmar Fey (DSD, 2020)

Direct state transfer in MLC based memristive ReRAM devices for ternary computing. - Dietmar Fey; John Reuben (ECCTD, 2020)

ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters. - Burkhard Ringlein; François Abel; Alexander Ditter; Beat Weiss; Christoph Hagleitner; Dietmar Fey (FCCM, 2020)

A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. - Johannes Knödtel; Markus Fritscher; Daniel Reiser; Dietmar Fey; Marco Breiling; Marc Reichenbach (MOCAST, 2020)

Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation. - Burkhard Ringlein; François Abel; Alexander Ditter; Beat Weiss; Christoph Hagleitner; Dietmar Fey (H2RC@SC, 2020)

Impact of Performance Estimation on Fast Processor Simulators. - Sebastian Rachuj; Dietmar Fey; Marc Reichenbach (SimuTools (2), 2020)

Memristoren für zukünftige Rechnersysteme. - Dietmar Fey; Wolfgang Karl; Theo Ungerer (Inform. Spektrum, 2020)

The allscale framework architecture. - Herbert Jordan; Philipp Gschwandtner; Peter Thoman; Peter Zangerl; Alexander Hirsch; Thomas Fahringer; Thomas Heller; Dietmar Fey (Parallel Comput., 2020)

Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. - Johannes Hofmann 001; Christie L. Alappat; Georg Hager; Dietmar Fey; Gerhard Wellein (Supercomput. Front. Innov., 2020)

A Case for Function-as-a-Service with Disaggregated FPGAs. - Burkhard Ringlein; François Abel; Dionysios Diamantopoulos; Beat Weiss; Christoph Hagleitner; Marc Reichenbach; Dietmar Fey (CLOUD, 2021)

Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic. - Dietmar Fey; John Reuben; Stefan Slesazeck (ICECS, 2021)

Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design. - Steffen Vaas; Peter Ulbrich; Christian Eichler; Peter Wägemann; Marc Reichenbach; Dietmar Fey (ISORC, 2021)

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. - John Reuben; Dietmar Fey (ISVLSI, 2021)

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. - Markus Fritscher; Johannes Knödtel; Daniel Reiser; Maen Mallah; Stefan Pechmann; Dietmar Fey; Marc Reichenbach (LASCAS, 2021)

Fault Tolerance in Heterogeneous Automotive Real-time Systems. - Johannes Lex; Ulrich Margull; Dietmar Fey; Ralph Mader (Echtzeit, 2021)

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. - Marc Reichenbach; Johannes Knödtel; Sebastian Rachuj; Dietmar Fey (IEEE Access, 2021)

Adaptation Strategies for Personalized Gait Neuroprosthetics. - Anne D. Koelewijn; Musa L. Audu; Antonio J. del Ama; Annalisa Colucci; Josep M. Font-Llagunes; Antonio Gogeascoechea; Sandra K. Hnat; Nathan S. Makowski; Juan C. Moreno 001; Mark J. Nandor; Roger D. Quinn; Marc Reichenbach; et al. (Frontiers Neurorobotics, 2021)

EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis. - Lars Schwenger; Philipp Holzinger; Dietmar Fey; Hector Gerardo Muñoz Hernandez; Marc Reichenbach (SAMOS, 2022)

Investigating SAMV Regarding its Suitability For FPGAs. - Farehe Giahi; Sebastian Rachuj; Dietmar Fey (SOCC, 2022)

Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture. - Shima Hosseinzadeh; Amirhossein Parvaresh; Dietmar Fey (ARCS, 2023)

DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs. - Burkhard Ringlein; François Abel; Dionysios Diamantopoulos; Beat Weiss; Christoph Hagleitner; Dietmar Fey (EDGE, 2023)

A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories. - John Reuben; Dietmar Fey; Stefan Slesazeck (MOCAST, 2023)

Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study. - Amirhossein Parvaresh; Shima Hosseinzadeh; Dietmar Fey (NANOARCH, 2023)

Hyper Dimensional Computing with Ferroelectric Tunneling Junctions. - Stefan Slesazeck; Suzanne Lancaster; John Reuben; Shima Hosseinzadeh; Dietmar Fey; Thomas Mikolajick (NANOARCH, 2023)

Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing. - Johannes Kliemt; Dietmar Fey (SIMULTECH, 2023)

Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures. - Burkhard Ringlein; François Abel; Dionysios Diamantopoulos; Beat Weiss; Christoph Hagleitner; Dietmar Fey (IEEE Comput. Archit. Lett., 2023)

Memristive computing in Germany. - Dietmar Fey (it Inf. Technol., 2023)

Optimizing multi-level ReRAM memory for low latency and low energy consumption. - Shima Hosseinzadeh; Marius Klemm; Georg Fischer 001; Dietmar Fey (it Inf. Technol., 2023)

Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level. - Johannes Kliemt; Markus Fritscher; Dietmar Fey (ARCS, 2024)

Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory. - Shima Hosseinzadeh; Suzanne Lancaster; Amirhossein Parvaresh; Cláudia Silva; Dietmar Fey (DSD, 2024)

Area-Efficient Digital Design Using RRAM-CMOS Standard Cells. - Markus Fritscher; Max Uhlmann; Philip Ostrovskyy; Daniel Reiser; Junchao Chen 001; Markus Andreas Schubert; Carsten Schulze; Gerhard Kahmen; Dietmar Fey; Marc Reichenbach; Milos Krstic; Christian Wenger (ISVLSI, 2024)

On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory. - John Reuben; Suzanne Lancaster; Dietmar Fey; Stefan Slesazeck (NorCAS, 2024)

HyFAR: A hypervisor-based fault tolerance approach for heterogeneous automotive real-time systems. - Johannes Lex; Ulrich Margull; Ralph Mader; Dietmar Fey (J. Syst. Archit., 2024)

ExTern: Boosting RISC-V core performance using ternary encoding. - Farhad Ebrahimi-Azandaryani; Dietmar Fey (Microprocess. Microsystems, 2024)

FPGA Implementation of a Real-Time Application Based on RISC-V Cores. - Amr Abdelhafez; Farhad EbrahimiAzandaryani; Maurizio Bianconi; Dietmar Fey (SSD, 2025)

CSD-Driven Speedup in RISC-V Processor. - Farhad EbrahimiAzandaryani; Dietmar Fey (DASIP, 2025)

Specification of Generic Memristor-Based Crossbar Architectures for In-Memory Computing. - Benjamin Seiler; Dietmar Fey (MOCAST, 2025)

RISC-V CPU Design Using RRAM-CMOS Standard Cells. - Markus Fritscher; Max Uhlmann; Philip Ostrovskyy; Daniel Reiser; Junchao Chen 001; Jianan Wen; Carsten Schulze; Gerhard Kahmen; Dietmar Fey; Marc Reichenbach; Milos Krstic; Christian Wenger (IEEE Trans. Very Large Scale Integr. Syst., 2025)