An ADSL-RT full-rate analog front end IC with integrated line driver. - Hubert Weinberger; Andreas Wiesbauer; Christian Fleischhacker; Jörg Hauptmann; Thomas Ferianz; Michael Staber; Dietmar Sträußnigg; Berthold Seger (IEEE J. Solid State Circuits, 2002)

Correlated discrete disturbers cancelation in data communication systems. - David Schwingshackl; Dietmar Straeussnigg (EUSIPCO, 2006)

Clock jitter compensation for current steering DACs. - Andreas Wiesbauer; Dietmar Sträußnigg; Richard Gaggl; Martin Clara; Luis Hernández 003; Daniel Gruber (ISCAS, 2006)

Comparative study of linear and non-linear integrated control schemes applied to a Buck converter for mobile applications. - Robert Priewasser; Matteo Agostinelli; Stefano Marsili; Dietmar Sträußnigg; Mario Huemer (Elektrotech. Informationstechnik, 2010)

A time-encoding CMOS capacitive sensor readout circuit with flicker noise reduction. - Fernando Cardes; Luis Hernández 003; Javier Escobar; Andreas Wiesbauer; Dietmar Straeussnigg; Richard Gaggl (MWSCAS, 2014)

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. - Fernando Cardes; Ruzica Jevtic; Luis Hernández 003; Andreas Wiesbauer; Dietmar Sträußnigg; Richard Gaggl (ISCAS, 2015)

A noise coupled ΣΔ architecture using a Non Uniform Quantizer. - Juan A. Torreño; Susana Patón; Laura Conesa-Peraleja; Luis Hernández 003; Dietmar Straeussnigg (NORCAS, 2015)

Signal boosting to extend the bandwidth of oversampled converters. - Laura Conesa-Peraleja; Susana Patón; Dietmar Straeussnigg; Andreas Wiesbauer (ICECS, 2016)

9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNR. - Elmar Bach; Richard Gaggl; Luca Sant; Cesare Buffa; Snezana Stojanovic; Dietmar Straeussnigg; Andreas Wiesbauer (ISSCC, 2017)

Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators. - Pablo Vera; Susana Patón; Dietmar Straeussnigg (ISCAS, 2019)

A 69dBA-730µW Silicon Microphone System with Ultra & Infra-Sound Robustness. - Jose Luis Ceballos; Christopher Rogi; Fulvio Ciciotti; Cesare Buffa; Dietmar Straeussnigg; Andreas Wiesbauer (ESSCIRC, 2022)

Optimal reconfiguration instant in ΣΔ Modulators. - Pablo Vera; Dietmar Straeussnigg; Victor Medina; Luis Hernández 003; Susana Patón (ISCAS, 2022)

Towards Ultra-Low Power Consumption VAD Architectures with Mixed Signal Circuits. - Yukai Shen; Dietmar Straeussnigg; Eric Gutierrez (ISCAS, 2023)

A 70dBA-460μW Companding Digital Silicon Microphone with Programmable Acoustic Overload Point and MEMS Asymmetry Robustness. - Jose Luis Ceballos; Fulvio Ciciotti; Christopher Rogi; Alessandro Caspani; Luca Sant; Dietmar Straeussnigg; Andreas Wiesbauer; Simon Gruenberger; Chin Yeong Koh; Chern Sia Phillip Lim (ISCAS, 2024)

Time-Encoded Mostly Digital Feature Extraction for Voice Activity Detection Tasks. - Yukai Shen; Carlos Perez; Dietmar Straeussnigg; Eric Gutierrez (ISCAS, 2024)

Design of a spurious-free VCO-ADC for Audio. - Andrés Quintero; Carlos Perez; Pedro Amaral; Dietmar Straeussnigg; Andreas Wiesbauer (ISCAS, 2025)