An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory. - Dieu Van Dinh; Virginia Rabitoy (ITC, 2000)

Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities. - Darren Aaberge; Ken Mockler; Dieu Van Dinh; Raoul Belleau; Tim Donovan; Reid Hewlitt (VTS, 2005)

A Design Approach to Reduce Test Time on SOC Memories. - Prokash Ghosh; Dieu Van Dinh; Misal Varma (SoCC, 2021)