CMOS logic gate performance variability related to transistor network arrangements. - Digeorgia N. da Silva; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2009)

Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology. - Digeorgia N. da Silva; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2010)