A Hardware Generator for Posit Arithmetic and its FPGA Prototyping. - Diksha Shekhawat; Apoorva Jangir; Jai Gopal Pandey (VDAT, 2021)

LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (APCCAS, 2023)

PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations. - Diksha Shekhawat; Jugal Gandhi; M. Santosh; Jai Gopal Pandey (CoNGA, 2023)

Security Evaluation of Lightweight SBoxes. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (iSES, 2023)

Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (Comput. Secur., 2023)

Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jaya Dofe; Jai Gopal Pandey (ATS, 2024)

Emerging Frontiers and Limitations of Logic Locking for Secure IC Design. - Jugal Gandhi; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (MCSoC, 2024)

SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking. - Jugal Gandhi; Rishi Agarwal; Anish Mall; Diksha Shekhawat; M. Santosh; Jai Gopal Pandey (VLSID, 2024)

Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher. - Kartik Jhawar; Jugal Gandhi; Diksha Shekhawat; Aniket Upadhyay; Avadh Harkishanka; Nitin Chaturvedi; M. Santosh; Jai Gopal Pandey (J. Real Time Image Process., 2024)

DyLock: A Dynamic Key-based SAT and Structural Attacks Resilient Low-overhead Logic Locking. - Jugal Gandhi; Diksha Shekhawat; Jaya Dofe; Jai Gopal Pandey (ISCAS, 2025)

SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation. - Jugal Gandhi; Nikhil Handa; Abhay Nayak; Diksha Shekhawat; M. Santosh; Jaya Dofe; Jai Gopal Pandey (VLSID, 2025)