A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. - Suhwan Kim 002; Vaibhav A. Vaidya; Christopher Schaef; Andrew Lines; Harish Krishnamurthy; Sheldon Weng; Xiaosen Liu; Dileep Kurian; Tanay Karnik; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2018)

A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. - Vinayak Honkote; Dileep Kurian; Sriram Muthukumar; Dibyendu Ghosh; Satish Yada; Kartik Jain; Bradley Jackson; Ilya Klotchkov; Mallikarjuna Rao Nimmagadda; Shreela Dattawadkar; Pranjali Deshmukh; Ankit Gupta 011; et al. (ISSCC, 2019)

Self-Powered IOT System for Edge Inference. - Dileep Kurian; Tanay Karnik; Saksham Soni; Saransh Chhabra; Suhwan Kim 002; Jaykant Timbadiya; Ankit Gupta 011; Krishnan Ravichandran; Mukesh Bhartiya; Angela Nicoara (ISQED, 2020)

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding. - Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Dileep Kurian; Indranil Chakraborty; Sirisha Rani Kale; Nilesh Jain; Tanay Karnik; Ravi R. Iyer 001; Anuradha Srinivasan (DATE, 2021)

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation. - Srivatsa Srinivasa; Akshay Krishna Ramanathan; Jainaveen Sundaram; Dileep Kurian; Srinivasan Gopal; Nilesh Jain; Anuradha Srinivasan; Ravi R. Iyer 001; Vijaykrishnan Narayanan; Tanay Karnik (ISQED, 2021)

A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology. - Jong Seok Park 001; Sushil Subramanian; Lester Lampert; Todor Mladenov; Ilya Klotchkov; Dileep Kurian; Esdras Juárez-Hernández; Brando Perez Esparza; Sirisha Rani Kale; K. T. Asma Beevi; Shavindra P. Premaratne; Thomas Watson 006; et al. (ISSCC, 2021)

A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits. - Jongseok Park 001; Sushil Subramanian; Lester Lampert; Todor Mladenov; Ilya Klotchkov; Dileep Kurian; Esdras Juarez Hernandez; Brando Perez Esparza; Sirisha Rani Kale; K. T. Asma Beevi; Shavindra P. Premaratne; Thomas Watson 006; et al. (IEEE J. Solid State Circuits, 2021)

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. - Ragh Kuttappa; Baris Taskin; Vinayak Honkote; Satish Yada; Jainaveen Sundaram; Dileep Kurian; Tanay Karnik; Anuradha Srinivasan (ISCAS, 2022)

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. - Srivatsa Rangachar Srinivasa; Jainaveen Sundaram Priya; Dileep Kurian; Erika Ramirez Lozano; Satish Yada; Saransh Chhabra; Kamakhya Prasad Sahu; Paolo A. Aseron; Ronald Kalim; Anuradha Srinivasan; Tanay Karnik (ISQED, 2022)

A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. - Vinayak Honkote; Ragh Kuttappa; Jainaveen Sundaram; Satish Yada; Chinnusamy Kalimuthu; Juhi Patil; Richard Lee; Cristan Paulino; Paolo A. Aseron; Trang Nguyen; Amreesh Rao; Dileep Kurian; et al. (VLSI Technology and Circuits, 2024)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. - Srivatsa Rangachar Srinivasa; Prerna Budhkar; Gauthaman Murali; Vui Seng Chua; Paolo A. Aseron; Vinayak Honkote; Ravi R. Iyer 001; Nilesh Jain; Dileep John Kurian; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)