CLEO: a CMOS layout generator. - Antun Domic; Samuel Levitin; Nathan Phillips; Channeary Thai; Thomas R. Shiple; Dilip Bhavsar; Clint Bissel (ICCAD, 1989)

A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability Access. - Dilip Bhavsar (VLSI Design, 1998)

Lateral coupling faults in multi-ported register files and methods for their testing. - Dilip Bhavsar; Michael Lohmiller; Pankaj Pant (VTS, 2016)