Self-Testing by Polynomial Division. - Dilip K. Bhavsar; Richard W. Heckelman (ITC, 1981)

Design For Test Calculus: An algorithm for DFT rules checking. - Dilip K. Bhavsar (DAC, 1983)

Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? - Dilip K. Bhavsar; Balakrishnan Krishnamurthy (ITC, 1984)

"Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test. - Dilip K. Bhavsar (ITC, 1985)

A New Economical Implementation for Scannable Flip-Flops in MOS. - Dilip K. Bhavsar (IEEE Des. Test, 1986)

An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. - Dilip K. Bhavsar (ITC, 1991)

Testing Interconnections to Static RAMs. - Dilip K. Bhavsar (IEEE Des. Test Comput., 1991)

Testability Strategy of the ALPHA AXP 21164 Microprocessor. - Dilip K. Bhavsar; John H. Edmondson (ITC, 1994)

Alpha 21164 Testability Strategy. - Dilip K. Bhavsar; John H. Edmondson (IEEE Des. Test Comput., 1997)

Testability access of the high speed test features in the Alpha 21264 microprocessor. - Dilip K. Bhavsar; David R. Akeson; Michael K. Gowan; Daniel B. Jackson (ITC, 1998)

A highly testable and diagnosable fabrication process test chip. - Dilip K. Bhavsar; Ugonna Echeruo; David R. Akeson; William J. Bowhill (ITC, 1998)

ITC 97 Panel Sessions. - Dilip K. Bhavsar; Yervant Zorian (IEEE Des. Test Comput., 1998)

An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. - Dilip K. Bhavsar (ITC, 1999)

ITC 99 Panels. - Dilip K. Bhavsar (IEEE Des. Test Comput., 1999)

Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. - Dilip K. Bhavsar (IEEE Des. Test Comput., 2000)

Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. - Dilip K. Bhavsar; Rishan Tan (VLSI Design, 2001)

Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. - Dilip K. Bhavsar (VTS, 2001)

Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. - Dilip K. Bhavsar; Richard A. Davies (VTS, 2002)

Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. - Joel Grodstein; Dilip K. Bhavsar; Vijay Bettada; Richard A. Davies (ICCD, 2003)

Testability Features of the Alpha 21364 Microprocessor. - Scott Erlanger; Dilip K. Bhavsar; Richard A. Davies (ITC, 2003)

A Built-in Self-Test Method for Write-only Content Addressable Memories. - Dilip K. Bhavsar (VTS, 2005)

Test access and the testability features of the Poulson multi-core Intel Itanium® processor. - Dilip K. Bhavsar; Steve Poehlman (ITC, 2011)

Harmony Widget for X-free scan testing. - Dilip K. Bhavsar (VTS, 2011)