A Novel Approach for On-line Testable Reversible Logic Circuit Desig. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (Asian Test Symposium, 2004)

A New Reversible Logic Gate and its Applications. - Dilip P. Vasudevan; Parag K. Lala (ESA/VLSI, 2004)

Online Testable Reversible Logic Circuit Design using NAND Blocks. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (DFT, 2004)

Logic implementation using a reversible gate. - Dilip P. Vasudevan; James Patrick Parkerson; Parag K. Lala (Circuits, Signals, and Systems, 2004)

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. - Jia Di; Parag K. Lala; Dilip P. Vasudevan (DFT, 2005)

A Technique for Modular Design of Self-Checking Carry-Select Adder. - Dilip P. Vasudevan; Parag K. Lala (DFT, 2005)

CMOS Realization of Online Testable Reversible Logic Gates. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (ISVLSI, 2005)

Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. - Jia Di; Dilip P. Vasudevan (DELTA, 2006)

Reversible-logic design with online testability. - Dilip P. Vasudevan; Parag K. Lala; Jia Di; James Patrick Parkerson (IEEE Trans. Instrum. Meas., 2006)

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. - Dilip P. Vasudevan; Parag K. Lala; James Patrick Parkerson (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Partial Scan Based Test Generation for Asynchronous Circuits. - Dilip P. Vasudevan; Aristides Efthymiou (DDECS, 2008)

Reversible online BIST using bidirectional BILBO. - Jiaoyan Chen 002; Dilip P. Vasudevan; Emanuel M. Popovici; Michel P. Schellekens (Conf. Computing Frontiers, 2010)

Static Average Case Power Estimation Technique for Block Ciphers. - Tingcong Ye; Dilip P. Vasudevan; Jiaoyan Chen 002; Emanuel M. Popovici; Michel P. Schellekens (DSD, 2010)

Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations. - Jiaoyan Chen 002; Dilip P. Vasudevan; Emanuel M. Popovici; Michel P. Schellekens; Peter Gillen (ICECS, 2010)

Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing. - Xiaodong Wang 020; Dilip P. Vasudevan; Hsien-Hsin S. Lee (3DIC, 2011)

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder. - Jiaoyan Chen 002; Dilip P. Vasudevan; Emanuel M. Popovici; Michel P. Schellekens (DSD, 2011)

Ultra Low Power Booth Multiplier Using Asynchronous Logic. - Jiaoyan Chen 002; Emanuel M. Popovici; Dilip P. Vasudevan; Michel P. Schellekens (ASYNC, 2012)

Ultra Low Power Asynchronous Charge Sharing Logic. - Jiaoyan Chen 002; Dilip P. Vasudevan; Michel P. Schellekens; Emanuel M. Popovici (J. Low Power Electron., 2012)

The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data. - Dilip P. Vasudevan; Andrew A. Chien (ACM Great Lakes Symposium on VLSI, 2015)

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. - Andrew A. Chien; Tung Thanh Hoang; Dilip P. Vasudevan; Yuanwei Fang; Amirali Shambayati (SIGARCH Comput. Archit. News, 2015)

A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems. - Abhishek Roy 002; Alicia Klinefelter; Farah B. Yahya; Xing Chen 004; Luisa Patricia Gonzalez-Guerrero; Christopher J. Lukas; Divya Akella Kamakshi; James Boley; Kyle Craig; Muhammad Faisal; Seunghyun Oh; Nathan E. Roberts; et al. (IEEE Trans. Biomed. Circuits Syst., 2015)

CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. - Dilip P. Vasudevan; George Michelogiannakis; David Donofrio; John Shalf (NANOARCH, 2017)

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. - Dilip P. Vasudevan; Anastasiia Butko; George Michelogiannakis; David Donofrio; John Shalf (ISC Workshops, 2017)

Boosted Race Trees for Low Energy Classification. - Georgios Tzimpragos; Advait Madhavan; Dilip Vasudevan; Dmitri B. Strukov; Timothy Sherwood (ASPLOS, 2019)

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. - Dilip P. Vasudevan; George Michelogiannakis; David Donofrio; John Shalf (ISPASS, 2019)

3D photonics as enabling technology for deep 3D DRAM stacking. - Sebastian Werner 002; Pouya Fotouhi; Xian Xiao; Marjan Fariborz; S. J. Ben Yoo; George Michelogiannakis; Dilip P. Vasudevan (MEMSYS, 2019)

A Computational Temporal Logic for Superconducting Accelerators. - Georgios Tzimpragos; Dilip Vasudevan; Nestan Tsiskaridze; George Michelogiannakis; Advait Madhavan; Jennifer Volk; John Shalf; Timothy Sherwood (ASPLOS, 2020)

Language Support for Navigating Architecture Design in Closed Form. - Weilong Cui; Georgios Tzimpragos; Yu Tao; Joseph McMahan; Deeksha Dangwal; Nestan Tsiskaridze; George Michelogiannakis; Dilip P. Vasudevan; Timothy Sherwood (ACM J. Emerg. Technol. Comput. Syst., 2020)

SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC. - George Michelogiannakis; Darren Lyles; Patricia Gonzalez-Guerrero; Meriam Gay Bautista; Dilip Vasudevan; Anastasiia Butko (IPDPS, 2021)

In-sensor classification with boosted race trees. - Georgios Tzimpragos; Advait Madhavan; Dilip Vasudevan; Dmitri B. Strukov; Timothy Sherwood (Commun. ACM, 2021)

Temporal Computing With Superconductors. - Georgios Tzimpragos; Jennifer Volk; Dilip Vasudevan; Nestan Tsiskaridze; George Michelogiannakis; Advait Madhavan; John Shalf; Timothy Sherwood (IEEE Micro, 2021)

Benefits of Optimistic Parallel Discrete Event Simulation for Network-on-Chip Simulation. - Maximilian H. Bremer; Nirmalendu Patra; Tan Nguyen 001; Dilip Vasudevan; Cy P. Chan (DS-RT, 2023)

BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture. - Hasita Veluri; Dilip Vasudevan (ISQED, 2024)

Skyrmion-Based Ternary CPU Design. - Korinna Frangias; Mi-Young Im; Hee-Sung Han; Dilip Vasudevan (ISVLSI, 2024)

InFormer: A High-throughput, Ultra-efficient In-memory Compute-based Floating-point Arithmetic Accelerator for Transformers. - Hasita Veluri; Dilip Vasudevan (ACM Great Lakes Symposium on VLSI, 2025)

An Error-Resilient Compute-in-Memory 3D FPCA Architecture for High-Performance Floating-Point Operations. - Hasita Veluri; Dilip Vasudevan (ISQED, 2025)