CoSA: Integrated Verification for Agile Hardware Design. - Cristian Mattarei; Makai Mann; Clark W. Barrett; Ross G. Daly; Dillon Huff; Pat Hanrahan (FMCAD, 2018)

Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures. - Dillon Huff; Pat Hanrahan (ReConFig, 2018)

Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

Type-directed scheduling of streaming accelerators. - David Durst; Matthew Feldman; Dillon Huff; David Akeley; Ross G. Daly; Gilbert Louis Bernstein; Marco Patrignani; Kayvon Fatahalian; Pat Hanrahan (PLDI, 2020)

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs. - Dillon Huff; Steve Dai; Pat Hanrahan (FCCM, 2021)

Compiling Halide Programs to Push-Memory Accelerators. - Qiaoyi Liu; Dillon Huff; Jeff Setter; Maxwell Strange; Kathleen Feng; Kavya Sreedhar; Ziheng Wang; Keyi Zhang; Mark Horowitz; Priyanka Raina; Fredrik Kjolstad (CoRR, 2021)

A polyhedral compiler for image processing hardware. - Dillon Huff (2021)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators. - Qiaoyi Liu; Jeff Setter; Dillon Huff; Maxwell Strange; Kathleen Feng; Mark Horowitz; Priyanka Raina; Fredrik Kjolstad (ACM Trans. Archit. Code Optim., 2023)