Energy and performance driven circuit design for emerging phase-change memory. - Dimin Niu; Yibo Chen; Xiangyu Dong 001; Yuan Xie 001 (ASP-DAC, 2010)

Impact of process variations on emerging memristor. - Dimin Niu; Yiran Chen 001; Cong Xu 002; Yuan Xie 001 (DAC, 2010)

Energy- and endurance-aware design of phase change memory caches. - Yongsoo Joo; Dimin Niu; Xiangyu Dong 001; Guangyu Sun 003; Naehyuck Chang; Yuan Xie 001 (DATE, 2010)

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. - Guangyu Sun 003; Yongsoo Joo; Yibo Chen; Dimin Niu; Yuan Xie 001; Yiran Chen 001; Hai Li 001 (HPCA, 2010)

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. - Yibo Chen; Dimin Niu; Yuan Xie 001; Krishnendu Chakrabarty (ICCAD, 2010)

Low-power dual-element memristor based memory design. - Dimin Niu; Yiran Chen 001; Yuan Xie 001 (ISLPED, 2010)

A frequent-value based PRAM memory architecture. - Guangyu Sun 003; Dimin Niu; Jin Ouyang; Yuan Xie 001 (ASP-DAC, 2011)

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. - Cong Xu 002; Dimin Niu; Xiaochun Zhu; Seung-Hyuk Kang; Matt Nowak; Yuan Xie 001 (ICCAD, 2011)

Energy-efficient multi-level cell phase-change memory system with data encoding. - Jue Wang; Xiangyu Dong 001; Guangyu Sun 003; Dimin Niu; Yuan Xie 001 (ICCD, 2011)

F2BFLY: an on-chip free-space optical network with wavelength-switching. - Jin Ouyang; Chuan Yang; Dimin Niu; Yuan Xie 001; Zhiwen Liu (ICS, 2011)

Low power memristor-based ReRAM design with Error Correcting Code. - Dimin Niu; Yang Xiao 002; Yuan Xie 001 (ASP-DAC, 2012)

Design trade-offs for high density cross-point resistive memory. - Dimin Niu; Cong Xu 002; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (ISLPED, 2012)

Low-Power Design of Emerging Memory Technologies. - Yiran Chen 001; Hai Li 001; Yuan Xie 001; Dimin Niu (Handbook of Energy-Aware and Green Computing, 2012)

Understanding the trade-offs in multi-level cell ReRAM memory design. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (DAC, 2013)

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. - Dimin Niu; Cong Xu 002; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (ICCAD, 2013)

Low power multi-level-cell resistive memory design with incomplete data mapping. - Dimin Niu; Qiaosha Zou; Cong Xu 002; Yuan Xie 001 (ICCD, 2013)

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. - Cong Xu 002; Dimin Niu; Shimeng Yu; Yuan Xie 001 (ASP-DAC, 2014)

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. - Qiaosha Zou; Dimin Niu; Yan Cao; Yuan Xie 001 (ASP-DAC, 2014)

Reliability-aware cross-point resistive memory design. - Cong Xu 002; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2014)

Architecting 3D vertical resistive memory for next-generation storage systems. - Cong Xu 002; Pai-Yu Chen; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ICCAD, 2014)

SBAC: a statistics based cache bypassing method for asymmetric-access caches. - Chao Zhang 007; Guangyu Sun 003; Peng Li 031; Tao Wang 004; Dimin Niu; Yiran Chen 001 (ISLPED, 2014)

Overcoming the challenges of crossbar resistive memory architectures. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Rajeev Balasubramonian; Tao Zhang 032; Shimeng Yu; Yuan Xie 001 (HPCA, 2015)

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. - Cong Xu 002; Yang Zheng; Dimin Niu; Xiaochun Zhu; Seung-Hyuk Kang; Yuan Xie 001 (IEEE Trans. Multi Scale Comput. Syst., 2015)

Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. - Cong Xu 002; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

DRISA: a DRAM-based reconfigurable in-situ accelerator. - Shuangchen Li; Dimin Niu; Krishna T. Malladi; Hongzhong Zheng; Bob Brennan; Yuan Xie 001 (MICRO, 2017)

FlashStorageSim: Performance Modeling for SSD Architectures. - Krishna T. Malladi; Mu-Tien Chang; Dimin Niu; Hongzhong Zheng (NAS, 2017)

DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. - Mingyu Gao 001; Christina Delimitrou; Dimin Niu; Krishna T. Malladi; Hongzhong Zheng; Bob Brennan; Christos Kozyrakis (IEEE Micro, 2017)

Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. - Mu-Tien Chang; I. Stephen Choi; Dimin Niu; Hongzhong Zheng (ACM Great Lakes Symposium on VLSI, 2018)

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. - Shuangchen Li; Alvin Oliver Glova; Xing Hu 001; Peng Gu; Dimin Niu; Krishna T. Malladi; Hongzhong Zheng; Bob Brennan; Yuan Xie 001 (MICRO, 2018)

GraphQ: Scalable PIM-Based Graph Processing. - Youwei Zhuo; Chao Wang 051; Mingxing Zhang; Rui Wang 014; Dimin Niu; Yanzhi Wang; Xuehai Qian (MICRO, 2019)

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. - Zhao Wang; Yijin Guan; Guangyu Sun 003; Dimin Niu; Yuhao Wang 002; Hongzhong Zheng; Yinhe Han 001 (ACA, 2020)

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. - Zhenhua Zhu; Hanbo Sun; Kaizhong Qiu; Lixue Xia; Gokul Krishnan; Guohao Dai; Dimin Niu; Xiaoming Chen 003; Xiaobo Sharon Hu; Yu Cao 001; Yuan Xie 001; Yu Wang 002; et al. (ACM Great Lakes Symposium on VLSI, 2020)

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture. - Peng Gu; Xinfeng Xie; Yufei Ding 001; Guoyang Chen; Weifeng Zhang 003; Dimin Niu; Yuan Xie 001 (ISCA, 2020)

MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing. - Xinfeng Xie; Peng Gu; Yufei Ding 001; Dimin Niu; Hongzhong Zheng; Yuan Xie 001 (CoRR, 2021)

Area Efficient Pattern Representation of Binary Neural Networks on RRAM. - Feng Wang 046; Guojie Luo; Guang-Yu Sun 003; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (J. Comput. Sci. Technol., 2021)

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. - Peng Gu; Xinfeng Xie; Shuangchen Li; Dimin Niu; Hongzhong Zheng; Krishna T. Malladi; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. - Feng Wang 046; Guojie Luo; Guangyu Sun 003; Jiaxi Zhang 001; Jinfeng Kang; Yuhao Wang 002; Dimin Niu; Hongzhong Zheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. - Xingchen Li; Bingzhe Wu; Guangyu Sun 003; Zhe Zhang 006; Zhihang Yuan; Runsheng Wang; Ru Huang 001; Dimin Niu; Hongzhong Zheng; Zhichao Lu; Liang Zhao; Meng-Fan Marvin Chang; et al. (HPCA, 2022)

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Nianxiong Tan; Xiaopeng Yu 002; Hongzhong Zheng; Jianyi Meng; Xiaolang Yan; Yuan Xie 001 (ICPADS, 2022)

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. - Shuangchen Li; Dimin Niu; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Tianchan Guan; Yijin Guan; Heng Liu; Linyong Huang; Zhaoyang Du; Fei Xue; Yuanwei Fang; et al. (ISCA, 2022)

184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. - Dimin Niu; Shuangchen Li; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Yijin Guan; Tianchan Guan; Fei Sun; Fei Xue; Lide Duan; Yuanwei Fang; Hongzhong Zheng; et al. (ISSCC, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Linyong Huang; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. - Linyong Huang; Zhe Zhang 006; Shuangchen Li; Dimin Niu; Yijin Guan; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. - Xingchen Li; Zhihang Yuan; Yijin Guan; Guangyu Sun 003; Tao Zhang 032; Rongshan Wei; Dimin Niu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. - Zhiyao Li; Jiaxiang Li; Taijie Chen; Dimin Niu; Hongzhong Zheng; Yuan Xie 001; Mingyu Gao 001 (ASPLOS (2), 2023)

NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction. - Cong Li; Zhe Zhou 002; Xingchen Li; Guangyu Sun 003; Dimin Niu (DAC, 2023)

CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product. - Xuanle Ren; Zhaohui Chen; Zhen Gu; Yanheng Lu; Ruiguang Zhong; Wen-Jie Lu; Jiansong Zhang 001; Yichi Zhang; Hanghang Wu; Xiaofu Zheng; Heng Liu; Tingqiang Chu; et al. (DAC, 2023)

TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. - Zheng Qu; Dimin Niu; Shuangchen Li; Hongzhong Zheng; Yuan Xie 001 (MICRO, 2023)

MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing. - Xinfeng Xie; Peng Gu; Yufei Ding 001; Dimin Niu; Hongzhong Zheng; Yuan Xie 008 (ACM Trans. Archit. Code Optim., 2023)

Accelerating Distributed GNN Training by Codes. - Yanhong Wang; Tianchan Guan; Dimin Niu; Qiaosha Zou; Hongzhong Zheng; Chuanjin Richard Shi; Yuan Xie 001 (IEEE Trans. Parallel Distributed Syst., 2023)

MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. - Zhenhua Zhu; Hanbo Sun; Tongxin Xie; Yu Zhu; Guohao Dai; Lixue Xia; Dimin Niu; Xiaoming Chen 003; Xiaobo Sharon Hu; Yu Cao 001; Yuan Xie 001; Huazhong Yang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms. - Yu Zou; Yiran Li; Sheng Wang 011; Le Su; Zhen Gu; Yanheng Lu; Yijin Guan; Dimin Niu; Mingyu Gao 001; Yuan Xie 001; Feifei Li 001 (ASPLOS (4), 2024)

Zero-Shot Structure-Preserving Diffusion Model for High Dynamic Range Tone Mapping. - Ruoxi Zhu; Shusong Xu; Peiye Liu; Sicheng Li 001; Yanheng Lu; Dimin Niu; Zihao Liu; Zihao Meng; Zhiyong Li 016; Xinhua Chen; Yibo Fan (CVPR, 2024)

HydraRPC: RPC in the CXL Era. - Teng Ma 006; Zheng Liu; Chengkun Wei; Jialiang Huang; Youwei Zhuo; Haoyu Li; Ning Zhang; Yijin Guan; Dimin Niu; Mingxing Zhang; Tao Ma 006 (USENIX ATC, 2024)

Unicorn: Unified Neural Image Compression with One Number Reconstruction. - Qi Zheng 004; Haozhi Wang; Zihao Liu; Jiaming Liu; Peiye Liu; Zhijian Hao; Yanheng Lu; Dimin Niu; Jinjia Zhou; Ming-e Jing; Yibo Fan (CoRR, 2024)

CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing. - Zhao Wang; Yiqi Chen; Cong Li; Yijin Guan; Dimin Niu; Tianchan Guan; Zhaoyang Du; Xingda Wei; Guangyu Sun 003 (ASPLOS (2), 2025)

Frequency-Biased Synergistic Design for Image Compression and Compensation. - Jiaming Liu; Qi Zheng 004; Zihao Liu; Yilian Zhong; Peiye Liu; Tao Liu 023; Shusong Xu; Yanheng Lu; Sicheng Li 001; Dimin Niu; Yibo Fan (CVPR, 2025)

H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference. - Cong Li; Yihan Yin; Xintong Wu; Jingchen Zhu; Zhutianya Gao; Dimin Niu; Qiang Wu 012; Xin Si; Yuan Xie 001; Chen Zhang 001; Guangyu Sun 003 (ISCA, 2025)

Enabling Efficient Transaction Processing on CXL-Based Memory Sharing. - Zhao Wang; Yiqi Chen; Cong Li; Dimin Niu; Tianchan Guan; Zhaoyang Du; Xingda Wei; Guangyu Sun 003 (CoRR, 2025)

SAFE: A Scalable Homomorphic Encryption Accelerator for Vertical Federated Learning. - Zhaohui Chen; Zhen Gu; Yanheng Lu; Xuanle Ren; Ruiguang Zhong; Wen-Jie Lu; Jiansong Zhang 001; Yichi Zhang; Hanghang Wu; Xiaofu Zheng; Heng Liu; Tingqiang Chu; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Tightly Coupled AI-ISP Vision Processor. - Hao Zhang 126; Sicheng Li 001; Yupeng Gui; Zhiyong Li 016; Shusong Xu; Yanheng Lu; Dimin Niu; Hongzhong Zheng; Yen-Kuang Chen; Yuan Xie 001; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2025)