A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. - Sylvain Clerc; Fady Abouzeid; Gilles Gasiot; David Gauthier; Dimitri Soussan; Philippe Roche (ICICDT, 2012)

A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. - Dimitri Soussan; Alexandre Valentian; Sylvain Majcherczak; Marc Belleville (ICICDT, 2012)

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. - Fady Abouzeid; Sylvain Clerc; Cyril Bottoni; Benjamin Coeffic; Jean-Marc Daveau; Damien Croain; Gilles Gasiot; Dimitri Soussan; Philippe Roche (ESSCIRC, 2015)

Muons and thermal neutrons SEU characterization of 28nm UTBB FD-SOI and Bulk eSRAMs. - Gilles Gasiot; Dimitri Soussan; Jean-Luc Autran; Victor Malherbe; Philippe Roche (IRPS, 2015)

Alpha soft error rate of FDSOI 28 nm SRAMs: Experimental testing and simulation analysis. - Victor Malherbe; Gilles Gasiot; Dimitri Soussan; Aurelien Patris; Jean-Luc Autran; Philippe Roche (IRPS, 2015)

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. - Sylvain Clerc; Mehdi Saligane; Fady Abouzeid; Martin Cochet; Jean-Marc Daveau; Cyril Bottoni; David Bol; Julien De Vos; Dominique Zamora; Benjamin Coeffic; Dimitri Soussan; Damien Croain; et al. (ISSCC, 2015)

30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation. - Fady Abouzeid; Christophe Bernicot; Sylvain Clerc; Jean-Marc Daveau; Gilles Gasiot; Daniel Noblet; Dimitri Soussan; Philippe Roche (ESSCIRC, 2016)