Dimitrios Stathis

Orcid: 0000-0002-5697-4272

Affiliations:
  • KTH Royal Institute of Technology, Stockholm, Sweden
  • Democritus University of Thrace, Xanthi, Greece


According to our database1, Dimitrios Stathis authored at least 28 papers between 2013 and 2024.

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Bibliography

2024
Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023
A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning.
IEEE Trans. Biomed. Circuits Syst., October, 2023

Clock tree generation by abutment in synchoros VLSI design.
Microprocess. Microsystems, 2023

DRRA-based Reconfigurable Architecture for Mixed-Radix FFT.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks.
J. Syst. Archit., 2022

Reducing the Configuration Overhead of the Distributed Two-level Control System.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Multi-objective Recurrent Neural Networks Optimization for the Edge - a Quantization-based Approach.
CoRR, 2021

Design and Implementation of Optimized Register File for Streaming Applications.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Synthesis of predictable global NoC by abutment in synchoros VLSI design.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.
J. Signal Process. Syst., 2020

NACU: A Non-Linear Arithmetic Unit for Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.
CoRR, 2019

Regional Clock Tree Generation by Abutment in Synchoros VLSI Design.
CoRR, 2019

Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
Massively Parallel Analog Computing: Ariadne's Thread Was Made of Memristors.
IEEE Trans. Emerg. Top. Comput., 2018

RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

2017
Can a reconfigurable architecture beat ASIC as a CNN accelerator?
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs.
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

2016
Alternative Architectures Toward Reliable Memristive Crossbar Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Live demonstration: XbarSim: An educational simulation tool for memristive crossbar-based circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

XbarSim: An educational simulation tool for memristive crossbar-based circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Solving AI problems with memristors: A case study for optimal "bin packing".
Proceedings of the 18th Panhellenic Conference on Informatics, 2014

Shortest Path Computing Using Memristor-Based Circuits and Cellular Automata.
Proceedings of the Cellular Automata, 2014

2013
Improved read voltage margins with alternative topologies for memristor-based crossbar memories.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013


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