Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. - Dimitrios Velenis; Kevin T. Tang; Ivan S. Kourtev; Victor Adler; Franklin Baez; Eby G. Friedman (ICECS, 2001)

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. - Dimitrios Velenis; Eby G. Friedman; Marios C. Papaefthymiou (ISCAS (4), 2001)

SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links. - Dimitrios Velenis; Dimitrios Kalogeras; Basil S. Maglaris (NETWORKING, 2002)

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. - Dimitrios Velenis; Kevin T. Tang; Ivan S. Kourtev; Victor Adler; Franklin Baez; Eby G. Friedman (J. Circuits Syst. Comput., 2002)

Reduced Delay Uncertainty in High Performance Clock Distribution Networks. - Dimitrios Velenis; Marios C. Papaefthymiou; Eby G. Friedman (DATE, 2003)

Buffer sizing for delay uncertainty induced by process variations. - Dimitrios Velenis; Ramyashree Sundaresha; Eby G. Friedman (ICECS, 2004)

Buffer Sizing for Crosstalk Induced Delay Uncertainty. - Dimitrios Velenis; Eby G. Friedman (PATMOS, 2004)

Clock tree layout design for reduced delay uncertainty. - Dimitrios Velenis; Marios C. Papaefthymiou; Eby G. Friedman (SoCC, 2004)

Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. - William R. Roberts; Dimitrios Velenis (PATMOS, 2005)

Effects of process and environmental variations on timing characteristics of clocked registers. - William R. Roberts; Dimitrios Velenis (ACM Great Lakes Symposium on VLSI, 2006)

Effects of crosstalk noise on H-tree clock distribution networks. - Itisha Chanodia; Dimitrios Velenis (ISCAS, 2006)

Power supply variation effects on timing characteristics of clocked registers. - William R. Roberts; Dimitrios Velenis (ISCAS, 2006)

Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. - Itisha Chanodia; Dimitrios Velenis (ISVLSI, 2006)

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees. - Boyan Semerdjiev; Dimitrios Velenis (ISCAS, 2007)

Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. - Boyan Semerdjiev; Dimitrios Velenis (VLSI Design, 2007)

Impact of 3D design choices on manufacturing cost. - Dimitrios Velenis; Michele Stucchi; Erik Jan Marinissen; Bart Swinnen; Eric Beyne (3DIC, 2009)

Effects of Parameter Variations on Timing Characteristics of Clocked Registers. - William R. Roberts; Dimitrios Velenis (J. Circuits Syst. Comput., 2009)

Cost effectiveness of 3D integration options. - Dimitrios Velenis; Erik Jan Marinissen; Eric Beyne (3DIC, 2010)

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. - Jouke Verbree; Erik Jan Marinissen; Philippe Roussel; Dimitrios Velenis (ETS, 2010)

3D integration: Circuit design, test, and reliability challenges. - Nikolaos Minas; Ingrid De Wolf; Erik Jan Marinissen; Michele Stucchi; Herman Oprins; Abdelkarim Mercha; Geert Van der Plas; Dimitrios Velenis; Pol Marchal (IOLTS, 2010)

Design issues and considerations for low-cost 3D TSV IC technology. - Geert Van der Plas; Paresh Limaye; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Domae Shinichi; Vladimir Cherman; et al. (ISSCC, 2010)

3D stacking using ultra thin dies. - Antonio La Manna; Dimitrios Velenis; Thibault Buisson; Mikael Detalle; Kenneth J. Rebibis; Wenqi Zhang; Eric Beyne (3DIC, 2011)

Development of cost-effective biocompatible packaging for microelectronic devices. - Karen Qian; Karl Malachowski; Paolo Fiorini; Dimitrios Velenis; Maaike Op de Beeck; Chris Van Hoof (EMBC, 2011)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. - Michele Stucchi; Dimitrios Velenis; Guruprasad Katti (IEEE Trans. Instrum. Meas., 2012)

Si interposer build-up options and impact on 3D system cost. - Dimitrios Velenis; Mikael Detalle; Erik Jan Marinissen; Eric Beyne (3DIC, 2013)

Processing active devices on Si interposer and impact on cost. - Dimitrios Velenis; Mikael Detalle; Geert Hellings; Mirko Scholz; Erik Jan Marinissen; Geert Van der Plas; Antonio La Manna; Andy Miller; Dimitri Linten; Eric Beyne (3DIC, 2015)

Active-lite interposer for 2.5 & 3D integration. - Geert Hellings; Mirko Scholz; Mikael Detalle; Dimitrios Velenis; Muriel de Potter de ten Broeck; C. Roda Neve; Y. Li; Stefaan Van Huylenbroeck; Shih-Hung Chen; Erik Jan Marinissen; Antonio La Manna; Geert Van der Plas; et al. (VLSIC, 2015)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Dimitrios Velenis; Joeri De Vos; Soon-Wook Kim; Jaber Derakhshandeh; Pieter Bex; Giovanni Capuz; Samuel Suhard; Kenneth June Rebibis; Stefaan Van Huylenbroeck; Erik Jan Marinissen; Alain Phommahaxay; Andy Miller; et al. (3DIC, 2019)

Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending. - Yefan Liu; Hao Yu; Gaspard Hiblot; Anastasiia Kruv; Marc Schaekers; Naoto Horiguchi; Dimitrios Velenis; Ingrid De Wolf (IRPS, 2019)

Fabrication Cost Analysis for Contactless 3-D ICs. - Ioannis A. Papistas; Vasilis F. Pavlidis; Dimitrios Velenis (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules. - Kenichi Miyaguchi; Yoojin Ban; Nicolas Pantano; Xiao Sun; Philippe Absil; Lieve Bogaerts; Peter Verheyen; Dimitrios Velenis; Marianna Pantouvaki; Joris Van Campenhout (ECOC, 2021)

(Why do we need) Wireless Heterogeneous Integration (anyway?). - Michaël Peeters; S. Sinha; Xiao Sun; Claude Desset; Giuseppe Gramegna; John Slabbekoorn; Pieter Bex; Nelson Pinho; Tomas Webers; Dimitrios Velenis; Andy Miller; Nadine Collaert; et al. (VLSI Technology and Circuits, 2022)

Efficient Backside Power Delivery for High-Performance Computing Systems. - Hesheng Lin; Geert Van der Plas; Xiao Sun; Dimitrios Velenis; Francky Catthoor; Rudy Lauwereins; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2022)

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. - Hesheng Lin; Dimitrios Velenis; Philip Nolmans; Xiao Sun; Francky Catthoor; Rudy Lauwereins; Geert Van der Plas; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Highly Optimized O-band Si Ring Modulators for Low-Power Hybrid CMOS-SiPho Transceivers. - Yoojin Ban; Minkyu Kim; Peter De Heyn; Davide Guermandi; Filippo Ferraro; Natarajan Rajasekaran; Peter Verheyen; Pieter Bex; Junwen He; Hakim Kobbi; Jeroen De Coster; Rafal Magdziak; et al. (OFC, 2023)

32×100 GHz WDM filter based on ultra-compact silicon rings with a high thermal tuning efficiency of 5.85 mW/π. - Qingzhong Deng; Ahmed H. El-Saeed; Alaa Elshazly; Guy Lepage; Chiara Marchese; Hakim Kobbi; Rafal Magdziak; Jeroen De Coster; Neha Singh; Marko Ersek Filipcic; Kristof Croes; Dimitrios Velenis; et al. (OFC, 2024)

Collective die-to-wafer bonding enabling low-loss evanescent coupling for optically interconnected System-on-Wafer. - Pengfei Xu; Junwen He; Koen Kennes; Anton Dvoretskii; Arnita Podpod; Guy Lepage; Negin Golshani; Rafal Magdziak; Swetanshu Bipul; Dieter Bode; Peter Verheyen; Maumita Chakrabarti; et al. (OFC, 2024)

Low-loss, multi-reticle stitched SiN waveguides for 300mm wafer-level optical interconnects. - Pengfei Xu; Chiara Marchese; Guy Lepage; Negin Golshani; Ruben Van Eenaeme; Andrea Mingardi; Joost Van Ongeval; Rafal Magdziak; Luc Halipre; Darko Trivkovic; Peter Verheyen; Maumita Chakrabarti; et al. (OFC, 2024)

Ultra-compact silicon rings with high thermal tuning efficiency demonstrated as an 8×400 GHz WDM filter. - Qingzhong Deng; Jeroen De Coster; Rafal Magdziak; Ahmed H. El-Saeed; Alaa Elshazly; Mehmet Oktay; Chiara Marchese; Guy Lepage; Javad Rahimi Vaskasi; Sadhishkumar Balakrishnan; Neha Singh; Dieter Bode; et al. (OFC, 2025)