Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. - Xrysovalantis Kavousianos; Dimitris Bakalis; Haridimos T. Vergos; Dimitris Nikolos; George Alexiou (DFT, 1999)

Low Power BIST for Wallace Tree-Based Fast Multipliers. - Dimitris Bakalis; Dimitris Nikolos; George Alexiou; Emmanouil Kalligeros; Haridimos T. Vergos (ISQED, 2000)

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ITC, 2000)

A novel reseeding technique for accumulator-based test pattern generation. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2001)

A New Reseeding Technique for LFSR-Based Test Pattern Generation. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (IOLTW, 2001)

On the Design of Self-Testing Checkers for Modified Berger Codes. - Stanislaw J. Piestrak; Dimitris Bakalis; Xrysovalantis Kavousianos (IOLTW, 2001)

On Accumulator-Based Bit-Serial Test Response Compaction Schemes. - Dimitris Bakalis; Dimitris Nikolos; Haridimos T. Vergos; Xrysovalantis Kavousianos (ISQED, 2001)

EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. - Dimitris Bakalis; Kostas Adaos; George Alexiou; Dimitris Nikolos; Dimitrios Lymperopoulos (IEEE International Workshop on Rapid System Prototyping, 2001)

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. - Dimitris Bakalis; Xrysovalantis Kavousianos; Haridimos T. Vergos; Dimitris Nikolos; G. Ph. Alexiou (VLSI Design, 2001)

Δομές ενσωματωμένου αυτοελέγχου για ψηφιακά κυκλώματα πολύ μεγάλης κλίμακας ολοκλήρωσης - Dimitris Bakalis (2001)

Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. - Giorgos Dimitrakopoulos; Dimitris Nikolos; Dimitris Bakalis (IOLTW, 2002)

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ISQED, 2002)

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (J. Electron. Test., 2002)

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. - Dimitris Bakalis; Emmanouil Kalligeros; Dimitris Nikolos; Haridimos T. Vergos; George Alexiou (J. Syst. Archit., 2002)

A new built-in TPG method for circuits with random patternresistant faults. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Low Power Testing by Test Vector Ordering with Vector Repetition. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos; Xrysovalantis Kavousianos (ISQED, 2004)

Scan Cell Ordering for Low Power BIST. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos (ISVLSI, 2004)

An Efficient Test Vector Ordering Method for Low Power Testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Maciej Bellos; Dimitris Nikolos (ISVLSI, 2004)

A core generator for arithmetic cores and testing structures with a network interface. - Dimitris Bakalis; Kostas Adaos; Dimitrios Lymperopoulos; Maciej Bellos; Haridimos T. Vergos; George Alexiou; Dimitris Nikolos (J. Syst. Archit., 2006)

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. - Haridimos T. Vergos; Dimitris Bakalis (DSD, 2008)

Efficient modulo 2n + 1 multi-operand adders. - Haridimos T. Vergos; Dimitris Bakalis; Costas Efstathiou (ICECS, 2008)

Combined SD-RNS Constant Multiplication. - Evangelos Vassalos; Dimitris Bakalis (DSD, 2009)

Efficient architectures for modulo 2n-1 squares. - Anastasia Spyrou; Dimitris Bakalis; Haridimos T. Vergos (DPS, 2009)

Novel modulo 2n+1 subtractors. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DPS, 2009)

Efficient partial scan cell gating for low-power scan-based testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ACM Trans. Design Autom. Electr. Syst., 2009)

Area-Efficient Multi-moduli Squarers for RNS. - Dimitris Bakalis; Haridimos T. Vergos (DSD, 2010)

SUT-RNS Forward and Reverse Converters. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (ISVLSI (Selected papers), 2010)

Fast modulo 2n+1 multi-operand adders and residue generators. - Haridimos T. Vergos; Dimitris Bakalis; Costas Efstathiou (Integr., 2010)

On Implementing Efficient Modulo 2n + 1 Arithmetic Components. - Haridimos T. Vergos; Dimitris Bakalis (J. Circuits Syst. Comput., 2010)

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSD, 2011)

On the use of double-LSB and signed-LSB encodings for RNS. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSP, 2011)

On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (Circuits Syst. Signal Process., 2011)

Efficient modulo 2n±1 squarers. - Dimitris Bakalis; Haridimos T. Vergos; Anastasia Spyrou (Integr., 2011)

SUT-RNS Residue-to-Binary Converters Design. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSD, 2012)

Area-time efficient multi-modulus adders and their applications. - Haridimos T. Vergos; Dimitris Bakalis (Microprocess. Microsystems, 2012)

CSD-RNS-based Single Constant Multipliers. - Evangelos Vassalos; Dimitris Bakalis (J. Signal Process. Syst., 2012)

Modulo 2n-2 arithmetic units. - Evangelos Vassalos; Dimitris Bakalis (EUROCON, 2013)

Reverse converters for RNSs with diminished-one encoded channels. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (EUROCON, 2013)

On the design of modulo 2n-1 cubing units. - Evangelos Vassalos; Dimitris Bakalis (ACM Great Lakes Symposium on VLSI, 2013)

RNS assisted image filtering and edge detection. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSP, 2013)

Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. - Haridimos T. Vergos; Dimitris Bakalis; A. Anastasiou (Circuits Syst. Signal Process., 2015)