Systematic t-error correcting all unidirectional error detecting codes. - Dimitris Nikolos; Nikolaos Gaitanis; George Philokyprou (Fehlertolerierende Rechensysteme, 1984)

Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. - Antonis M. Paschalis; Dimitris Nikolos; Constantine Halatsis (Aegean Workshop on Computing, 1986)

Systematic t-Error Correcting/All Unidirectional Error Detecting Codes. - Dimitris Nikolos; Nikolaos Gaitanis; George Philokyprou (IEEE Trans. Computers, 1986)

Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. - Dimitris Nikolos; Antonis M. Paschalis; George Philokyprou (IEEE Trans. Computers, 1988)

Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. - Antonis M. Paschalis; Dimitris Nikolos; Constantine Halatsis (IEEE Trans. Computers, 1988)

Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes. - Dimitris Nikolos (IEEE Trans. Computers, 1991)

Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t. - Dimitris Nikolos; Alexandros Krokos (IEEE Trans. Computers, 1992)

An efficient comparative concurrent Built-In Self-Test technique. - Ioannis Voyiatzis; Dimitris Nikolos; Antonis M. Paschalis; Constantinos Halatsis; Th. Haniotakis (Asian Test Symposium, 1995)

Accumulator-based BIST approach for stuck-open and delay fault testing. - Ioannis Voyiatzis; Antonis M. Paschalis; Dimitris Nikolos; Constantin Halatsis (ED&TC, 1995)

Testing combinational iterative logic arrays for realistic faults. - Dimitris Gizopoulos; Dimitris Nikolos; Antonis M. Paschalis (VTS, 1995)

Efficient fault tolerant cache memory design. - Haridimos T. Vergos; Dimitris Nikolos (Microprocess. Microprogramming, 1995)

On TSC Checkers for m-out-n Codes. - Vassilios V. Dimakopoulos; G. Sourtziotis; Antonis M. Paschalis; Dimitris Nikolos (IEEE Trans. Computers, 1995)

Efficient Totally Self-Checking Checkers for a Class of Borden Codes. - Th. Haniotakis; Antonis M. Paschalis; Dimitris Nikolos (IEEE Trans. Computers, 1995)

Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. - Dimitris Nikolos; Haridimos T. Vergos; Antonis Vazaios; Spyros Voulgaris (DFT, 1996)

C-Testable modified-Booth multipliers. - Dimitris Gizopoulos; Dimitris Nikolos; Antonis M. Paschalis; Constantin Halatsis (J. Electron. Test., 1996)

An efficient built-in self test method for robust path delay fault testing. - Ioannis Voyiatzis; Antonis M. Paschalis; Dimitris Nikolos; Constantin Halatsis (J. Electron. Test., 1996)

Testing CMOS combinational iterative logic arrays for realistic faults. - Dimitris Gizopoulos; Dimitris Nikolos; Antonis M. Paschalis (Integr., 1996)

Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. - Xrysovalantis Kavousianos; Dimitris Nikolos; G. Sidiropoulos (DFT, 1997)

Self-exercising self testing k-order comparators. - Xrysovalantis Kavousianos; Dimitris Nikolos (VTS, 1997)

C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. - Th. Haniotakis; Dimitris Nikolos; Y. Tsiatouhas (DFT, 1998)

R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. - Ioannis Voyiatzis; Antonis M. Paschalis; Dimitris Nikolos; Constantinos Halatsis (ITC, 1998)

Novel Single and Double Output TSC Berger Code Checkers. - Xrysovalantis Kavousianos; Dimitris Nikolos (VTS, 1998)

Self-Testing Embedded Two-Rail Checkers. - Dimitris Nikolos (J. Electron. Test., 1998)

Optimal Self-Testing Embedded Parity Checkers. - Dimitris Nikolos (IEEE Trans. Computers, 1998)

Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. - G. Sidiropoulos; Haridimos T. Vergos; Dimitris Nikolos (Asian Test Symposium, 1999)

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. - Dimitris Nikolos; Haridimos T. Vergos; Th. Haniotakis; Y. Tsiatouhas (DATE, 1999)

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. - Xrysovalantis Kavousianos; Dimitris Bakalis; Haridimos T. Vergos; Dimitris Nikolos; George Alexiou (DFT, 1999)

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. - Maciej Bellos; Dimitris Nikolos; Haridimos T. Vergos (EDCC, 1999)

On Path Delay Fault Testing of Multiplexer - Based Shifters. - Haridimos T. Vergos; Dimitris Nikolos; Y. Tsiatouhas; Th. Haniotakis; Michael Nicolaidis (Great Lakes Symposium on VLSI, 1999)

Path delay fault testing of Benes multistage interconnection networks. - Haridimos T. Vergos; Maciej Bellos; Dimitris Nikolos (ICECS, 1999)

Design and Analysis of On-Chip CPU Pipelined Caches. - C. Ninos; Haridimos T. Vergos; Dimitris Nikolos (VLSI, 1999)

Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. - A. Vasilliou; K. Gounaris; Kostas Adaos; D. Mitsainas; George Alexiou; Dimitris Nikolos (IEEE International Workshop on Rapid System Prototyping, 1999)

Modular TSC Checkers for Bose-Lin and Bose Codes. - Xrysovalantis Kavousianos; Dimitris Nikolos (VTS, 1999)

An Accumulator-Based BIST Approach for Two-Pattern Testing. - Ioannis Voyiatzis; Antonis M. Paschalis; Dimitris Nikolos; Constantin Halatsis (J. Electron. Test., 1999)

New efficient totally self-checking Berger code checkers. - Xrysovalantis Kavousianos; Dimitris Nikolos; G. Foukarakis; T. Gnardellis (Integr., 1999)

On the Yield of VLSI Processors with On-Chip CPU Cache. - Dimitris Nikolos; Haridimos T. Vergos (IEEE Trans. Computers, 1999)

A Versatile Built-In Self-Test Scheme for Delay Fault Testing. - Y. Tsiatouhas; Th. Haniotakis; Angela Arapoyanni; Dimitris Nikolos (DATE, 2000)

A Compact Built-In Current Sensor for IDDQ Testing. - Y. Tsiatouhas; Th. Haniotakis; Dimitris Nikolos (IOLTW, 2000)

Low Power BIST for Wallace Tree-Based Fast Multipliers. - Dimitris Bakalis; Dimitris Nikolos; George Alexiou; Emmanouil Kalligeros; Haridimos T. Vergos (ISQED, 2000)

On Testability of Multiple Precharged Domino Logic. - Th. Haniotakis; Y. Tsiatouhas; Dimitris Nikolos; Costas Efstathiou (ISQED, 2000)

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ITC, 2000)

High-Speed Parallel-Prefix Modulo 2n-1 Adders. - Lampros Kalampoukas; Dimitris Nikolos; Costas Efstathiou; Haridimos T. Vergos; John Kalamatianos (IEEE Trans. Computers, 2000)

Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes. - Xrysovalantis Kavousianos; Dimitris Nikolos; G. Sidiropoulos (VLSI Design, 2000)

High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. - Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (IEEE Symposium on Computer Arithmetic, 2001)

A novel reseeding technique for accumulator-based test pattern generation. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2001)

On the design of modulo 2n±1 adders. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (ICECS, 2001)

A New Reseeding Technique for LFSR-Based Test Pattern Generation. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (IOLTW, 2001)

Concurrent Detection of Soft Errors Based on Current Monitoring. - Y. Tsiatouhas; Th. Haniotakis; Dimitris Nikolos; Costas Efstathiou (IOLTW, 2001)

On Accumulator-Based Bit-Serial Test Response Compaction Schemes. - Dimitris Bakalis; Dimitris Nikolos; Haridimos T. Vergos; Xrysovalantis Kavousianos (ISQED, 2001)

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. - Haridimos T. Vergos; Dimitris Nikolos; Maciej Bellos; Costas Efstathiou (LATW, 2001)

EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. - Dimitris Bakalis; Kostas Adaos; George Alexiou; Dimitris Nikolos; Dimitrios Lymperopoulos (IEEE International Workshop on Rapid System Prototyping, 2001)

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. - Dimitris Bakalis; Xrysovalantis Kavousianos; Haridimos T. Vergos; Dimitris Nikolos; G. Ph. Alexiou (VLSI Design, 2001)

A ROMless LFSR Reseeding Scheme for Scan-based BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (Asian Test Symposium, 2002)

Test Set Embedding Based on Phase Shifters. - Maciej Bellos; Dimitrios Kagaris; Dimitris Nikolos (EDCC, 2002)

Ling adders in CMOS standard cell technologies. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (ICECS, 2002)

Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. - Giorgos Dimitrakopoulos; Dimitris Nikolos; Dimitris Bakalis (IOLTW, 2002)

A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. - Y. Tsiatouhas; Angela Arapoyanni; Dimitris Nikolos; Th. Haniotakis (IOLTW, 2002)

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ISQED, 2002)

Extending the Viability of IDDQ Testing in the Deep Submicron Era. - Y. Tsiatouhas; Th. Haniotakis; Dimitris Nikolos; Angela Arapoyanni (ISQED, 2002)

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (J. Electron. Test., 2002)

Guest Editorial. - Dimitris Nikolos; John P. Hayes; Michael Nicolaidis; Cecilia Metra (J. Electron. Test., 2002)

A new technique for IDDQ testing in nanometer technologies. - Y. Tsiatouhas; Yiannis Moisiadis; Th. Haniotakis; Dimitris Nikolos; Angela Arapoyanni (Integr., 2002)

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. - Dimitris Bakalis; Emmanouil Kalligeros; Dimitris Nikolos; Haridimos T. Vergos; George Alexiou (J. Syst. Archit., 2002)

Diminished-One Modulo 2n+1 Adder Design. - Haridimos T. Vergos; Costas Efstathiou; Dimitris Nikolos (IEEE Trans. Computers, 2002)

A new built-in TPG method for circuits with random patternresistant faults. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A Family of Parallel-Pre.x Modulo 2n - 1 Adders. - Giorgos Dimitrakopoulos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ASAP, 2003)

A highly regular multi-phase reseeding technique for scan-based BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2003)

Efficient modulo 2n+1 tree multipliers for diminished-1 operands. - Costas Efstathiou; Haridimos T. Vergos; Giorgos Dimitrakopoulos; Dimitris Nikolos (ICECS, 2003)

An Efficient BIST scheme for High-Speed Adders. - Dimitris G. Nikolos; Dimitris Nikolos; Haridimos T. Vergos; Costas Efstathiou (IOLTS, 2003)

An Efficient BIST scheme for High-Speed Adders. - Dimitris G. Nikolos; Dimitris Nikolos; Haridimos T. Vergos; Costas Efstathiou (IOLTS, 2003)

Virtual-scan: a novel approach for software-based self-testing of microprocessors. - Giorgos Dimitrakopoulos; Xrysovalantis Kavousianos; Dimitris Nikolos (ISCAS (5), 2003)

A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. - Giorgos Dimitrakopoulos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ISCAS (5), 2003)

Efficient BIST schemes for RNS datapaths. - Dimitris G. Nikolos; Dimitris Nikolos; Haridimos T. Vergos; Costas Efstathiou (ISCAS (5), 2003)

Efficient BIST schemes for RNS datapaths. - Dimitris G. Nikolos; Dimitris Nikolos; Haridimos T. Vergos; Costas Efstathiou (ISCAS (5), 2003)

Low Power Test Set Embedding Based on Phase Shifters. - Maciej Bellos; Dimitri Kagaris; Dimitris Nikolos (ISVLSI, 2003)

DV-TSE: Difference Vector Based Test Set Embedding. - Maciej Bellos; Xrysovalantis Kavousianos; Dimitris Nikolos; Dimitri Kagaris (VLSI-SOC, 2003)

Modulo 2n±1 Adder Design Using Select-Prefix Blocks. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (IEEE Trans. Computers, 2003)

Deterministic BIST for RNS Adders. - Haridimos T. Vergos; Dimitris Nikolos; Maciej Bellos; Costas Efstathiou (IEEE Trans. Computers, 2003)

A new test pattern generator for high defect coverage in a BIST environment. - Costas Laoudias; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2004)

Accumulator based Test-per-Scan BIST. - P. Karpodinis; Dimitri Kagaris; Dimitris Nikolos (IOLTS, 2004)

Low Power Testing by Test Vector Ordering with Vector Repetition. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos; Xrysovalantis Kavousianos (ISQED, 2004)

Scan Cell Ordering for Low Power BIST. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos (ISVLSI, 2004)

An Efficient Test Vector Ordering Method for Low Power Testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Maciej Bellos; Dimitris Nikolos (ISVLSI, 2004)

Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. - Giorgos Dimitrakopoulos; Pavlos Kolovos; P. Kalogerakis; Dimitris Nikolos (PATMOS, 2004)

Modified Booth Modulo 2n-1 Multipliers. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (IEEE Trans. Computers, 2004)

Fast Parallel-Prefix Modulo 2^n+1 Adders. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (IEEE Trans. Computers, 2004)

Multiphase BIST: a new reseeding technique for high test-data compression. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Deterministic Test Vector Compression / Decompression Using an Embedded Processor. - Maciej Bellos; Dimitris Nikolos (EDCC, 2005)

New architectures for modulo 2N - 1 adders. - Giorgos Dimitrakopoulos; Dimitris G. Nikolos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ICECS, 2005)

New architectures for modulo 2N - 1 adders. - Giorgos Dimitrakopoulos; Dimitris G. Nikolos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ICECS, 2005)

Power aware test-data compression for scan-based testing. - George Gekas; Dimitris Nikolos; Emmanouil Kalligeros; Xrysovalantis Kavousianos (ICECS, 2005)

Reseeding-Based Test Set Embedding with Reduced Test Sequences. - Emmanouil Kalligeros; D. Kaseridis; Xrysovalantis Kavousianos; Dimitris Nikolos (ISQED, 2005)

Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. - Giorgos Dimitrakopoulos; Dimitris Nikolos (PATMOS, 2005)

High-Speed Parallel-Prefix VLSI Ling Adders. - Giorgos Dimitrakopoulos; Dimitris Nikolos (IEEE Trans. Computers, 2005)

Efficient Diminished-1 Modulo 2^n+1 Multipliers. - Costas Efstathiou; Haridimos T. Vergos; Giorgos Dimitrakopoulos; Dimitris Nikolos (IEEE Trans. Computers, 2005)

An Energy-Delay Efficient Subword Permutation Unit. - Giorgos Dimitrakopoulos; Christos Mavrokefalidis; Costas Galanopoulos; Dimitris Nikolos (ASAP, 2006)

Efficient test-data compression for IP cores using multilevel Huffman coding. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (DATE, 2006)

Diophantine-Equation Based Arithmetic Test Set Embedding. - Dimitris Nikolos; Dimitrios Kagaris; Spyros Gidaros (IOLTS, 2006)

Fast bit permutation unit for media enhanced microprocessors. - Giorgos Dimitrakopoulos; Christos Mavrokefalidis; Costas Galanopoulos; Dimitris Nikolos (ISCAS, 2006)

Efficient Multiphase Test Set Embedding for Scan-based Testing. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (ISQED, 2006)

A core generator for arithmetic cores and testing structures with a network interface. - Dimitris Bakalis; Kostas Adaos; Dimitrios Lymperopoulos; Maciej Bellos; Haridimos T. Vergos; George Alexiou; Dimitris Nikolos (J. Syst. Archit., 2006)

On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. - Dimitrios Kagaris; P. Karpodinis; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Optimal Selective Huffman Coding for Test-Data Compression. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Computers, 2007)

Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Sorter Based Permutation Units for Media-Enhanced Microprocessors. - Giorgos Dimitrakopoulos; Christos Mavrokefalidis; Costas Galanopoulos; Dimitris Nikolos (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Testable Designs of Multiple Precharged Domino Circuits. - Themistoklis Haniotakis; Y. Tsiatouhas; Dimitris Nikolos; Costas Efstathiou (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. - Giorgos Dimitrakopoulos; Costas Galanopoulos; Christos Mavrokefalidis; Dimitris Nikolos (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Very Large Scale Integr. Syst., 2008)

LFSR-based test-data compression with self-stoppable seeds. - M. Koutsoupia; Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (DATE, 2009)

An Improved Search Method for Accumulator-Based Test Set Embedding. - Dimitris Nikolos; Dimitrios Kagaris; Samara Sudireddy; Spyros Gidaros (IEEE Trans. Computers, 2009)

Efficient partial scan cell gating for low-power scan-based testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ACM Trans. Design Autom. Electr. Syst., 2009)

Test data compression based on the reuse of parts of the dictionary entries. - Panagiotis Sismanoglou; Dimitris Nikolos (ICECS, 2011)

Enhancing dictionary based test data compression using the ATE repeat instruction. - Panagiotis Sismanoglou; Dimitris Nikolos (ICECS, 2013)

Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches. - Panagiotis Sismanoglou; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Spatial pattern prediction based management of faulty data caches. - Georgios Keramidas; Michail Mavropoulos; Anna Karvouniari; Dimitris Nikolos (DATE, 2014)

Test data compression based on reuse and bit-flipping of parts of dictionary entries. - Panagiotis Sismanoglou; Dimitris Nikolos (DDECS, 2014)

A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems. - Michail Mavropoulos; Georgios Keramidas; Dimitris Nikolos (DATE, 2015)

Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems. - Michail Mavropoulos; Georgios Keramidas; Grigorios Adamopoulos; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2015)

Preemptive built-in self-test for in-field structural testing. - Panagiotis Sismanoglou; Vlasis Pitsios; Dimitris Nikolos (ISQED, 2015)

Recovery of performance degradation in defective branch target buffers. - Filippos Filippou; Georgios Keramidas; Michail Mavropoulos; Dimitris Nikolos (IOLTS, 2016)

Conditional soft-edge flip-flop for SET mitigation. - Panagiotis Sismanoglou; Dimitris Nikolos (IOLTS, 2016)

Low capture power dictionary-based test data compression. - Panagiotis Sismanoglou; Dimitris Nikolos (ISQED, 2016)

A novel fault tolerant cache architecture based on orthogonal latin squares theory. - Filippos Filippou; Georgios Keramidas; Michail Mavropoulos; Dimitris Nikolos (DATE, 2018)

Run Time Management of Faulty Data Caches. - Michail Mavropoulos; Georgios Keramidas; Dimitris Nikolos (ETS, 2021)

Enabling efficient sub-block disabled caches using coarse grain spatial predictions. - Michail Mavropoulos; Georgios Keramidas; Dimitris Nikolos (Microprocess. Microsystems, 2022)

Improving the Performance Predictability of Faulty Data Caches. - Michail Mavropoulos; Georgios Keramidas; Dimitris Nikolos (EDCC, 2024)