STA for Mixed Cyclic, Acyclic Circuits. - Stavros Simoglou; Christos P. Sotiriou; Dimitris Valiantzas; Nikolaos Sketopoulos (ISVLSI, 2020)

Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. - Nikolaos Chatzivangelis; Dimitris Valiantzas; Christos P. Sotiriou; Iordanis Lilitsis (VLSI-SoC, 2022)

Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. - Christos Georgakidis; Dimitris Valiantzas; Stavros Simoglou; Iordanis Lilitsis; Nikolaos Chatzivangelis; Ilias Golfos; Marko S. Andjelkovic; Christos P. Sotiriou; Milos Krstic (DFT, 2023)