Static low power verification at transistor level for SoC design. - Jérôme Lescot; Vincent Bligny; Dina Medhat; Didier Chollat-Namy; Ziyang Lu; Sophie Billy; Mark Hofmann (ISLPED, 2012)

Physical verification flow for hierarchical analog ic design constraints. - Volker Meyer zu Bexten; Markus Tristl; Göran Jerke; Hartmut Marquardt; Dina Medhat (ASP-DAC, 2015)

Electrostatic Discharge Physical Verification of 2.5D/3D Integrated Circuits. - Dina Medhat; Mohamed Dessouky; DiaaEldin Khalil (ISQED, 2020)