Efficient Reconfiguration of WSI Arrays. - Dinesh Bhatia; Frank Thomson Leighton; Fillia Makedon (ICSI, 1990)

Restructuring wafers for maximum yield and some applications of WSI. - Dinesh Bhatia (SPDP, 1990)

Improved Algorithms for Routing on Two-Dimensional Grids. - Dinesh Bhatia; Frank Thomson Leighton; Fillia Makedon; Carolyn Haibt Norton (WG, 1992)

Pseudoexhaustive BIST for Sequential Circuits. - Dimitrios Kagaris; Spyros Tragoudas; Dinesh Bhatia (ICCD, 1993)

Mathematical model for routability analysis of FPGAs. - Dinesh Bhatia; Amit Chowdhary; Spyros Tragoudas (Great Lakes Symposium on VLSI, 1994)

Generalized segmented channel routing. - V. Shankar; Dinesh Bhatia (Great Lakes Symposium on VLSI, 1994)

Hierarchical Reconfiguration of VLSI/WSI Arrays. - Dinesh Bhatia; Ramesh Rajagopalan; Srinivas Katkoori (VLSI Design, 1994)

Detailed Routing of Multi-Terminal Nets in FPGAs. - Amit Chowdhary; Dinesh Bhatia (VLSI Design, 1994)

Resource requirements for field programmable interconnection chips. - Dinesh Bhatia; James Haralambides (VLSI Design, 1995)

Pseudo-exhaustive built-in TPG for sequential circuits. - Dimitrios Kagaris; Spyros Tragoudas; Dinesh Bhatia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

RACE: Reconfigurable and Adaptive Computing Environment. - Doug Smith; Dinesh Bhatia (FPL, 1996)

Multiway Partitioner for High Performance FPGA Based Board Architecture. - Vijayanand Sankarasubramanian; Dinesh Bhatia (ICCD, 1996)

Clock-Skew Constrained Cell Placement. - Natesan Venkateswaran; Dinesh Bhatia (VLSI Design, 1996)

Field-Programmable Gate Arrays. - Dinesh Bhatia (VLSI Design, 1996)

A Multi-Terminal Net Router for Field-Programmable Gate Arrays. - Dinesh Bhatia; Amit Chowdhary (VLSI Design, 1996)

Greedy Segmented Channel Router. - Dinesh Bhatia; V. Shankar (VLSI Design, 1996)

A constructive method for data path area estimation during high-level VLSI synthesis. - Natesan Venkateswaran; Anurag Gupta; Srinivas Katkoori; Dinesh Bhatia; Ranga Vemuri (ASP-DAC, 1997)

Performance Driven Floorplanning for FPGA Based Designs. - Jianzhong Shi; Dinesh Bhatia (FPGA, 1997)

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. - John Marty Emmert; Dinesh Bhatia (FPL, 1997)

Partitioning Under Timing and Area Constraints. - Gregory Tumbush; Dinesh Bhatia (ICCD, 1997)

Reconfigurable Computing. - Dinesh Bhatia (VLSI Design, 1997)

Macro Block Based FPGA Floorplanning. - Jianzhong Shi; Akash Randhar; Dinesh Bhatia (VLSI Design, 1997)

Temporal Partitioning and Scheduling for Reconfigurable Computing. - Karthikeya M. Gajjala Purna; Dinesh Bhatia (FCCM, 1998)

REACT: Reactive Environment for Runtime Reconfiguration. - Dinesh Bhatia; PariVallal Kannan; Kuldeep S. Simha; Karthikeya M. Gajjala Purna (FPL, 1998)

Fast Floorplanning for FPGAs. - John Marty Emmert; Akash Randhar; Dinesh Bhatia (FPL, 1998)

Partitioning in time: a paradigm for reconfigurable computing. - Karthikeya M. Gajjala Purna; Dinesh Bhatia (ICCD, 1998)

Clock-skew constrained placement for row based designs. - Natesan Venkateswaran; Dinesh Bhatia (ICCD, 1998)

Emulating Large Designs on Small Reconfigurable Hardware. - Karthikeya M. Gajjala Purna; Dinesh Bhatia (International Workshop on Rapid System Prototyping, 1998)

Timing Driven Multi-FPGA Board Partitioning. - Raghu Burra; Dinesh Bhatia (VLSI Design, 1998)

A Methodology for Fast FPGA Floorplanning. - John Marty Emmert; Dinesh Bhatia (FPGA, 1999)

NEBULA: A Partially and Dynamically Reconfigurable Architecture. - Dinesh Bhatia; Kuldeep S. Simha; PariVallal Kannan (FPL, 1999)

Tabu Search: Ultra-Fast Placement for FPGAs. - John Marty Emmert; Dinesh Bhatia (FPL, 1999)

Fast timing driven placement using tabu search. - John Marty Emmert; Dinesh Bhatia (ISCAS (1), 1999)

Clustering to improve bi-partition quality and run time. - Gregory Tumbush; Dinesh Bhatia (ISCAS (6), 1999)

Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. - Karthikeya M. Gajjala Purna; Dinesh Bhatia (IEEE Trans. Computers, 1999)

Bounds, designs and layouts for multi-terminal FPIC architectures. - Dinesh Bhatia; James Haralambides (Integr., 2000)

Resource requirements and layouts for field programmable interconnection chips. - Dinesh Bhatia; James Haralambides (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Tightly Integrated Placement and Routing for FPGAs. - PariVallal Kannan; Dinesh Bhatia (FPL, 2001)

fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (FPL, 2001)

On metrics for comparing routability estimation methods for FPGAs. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (DAC, 2002)

Rapid and Reliable Routability Estimation for FPGAs. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (FPL, 2002)

On Routing Demand and Congestion Estimation for FPGAs. - Shankar Balachandran; PariVallal Kannan; Dinesh Bhatia (ASP-DAC/VLSI Design, 2002)

Interconnect Estimation for FPGAs under Timing Driven Domains. - PariVallal Kannan; Dinesh Bhatia (ICCD, 2003)

A-priori wirelength and interconnect estimation based on circuit characteristics. - Shankar Balachandran; Dinesh Bhatia (SLIP, 2003)

On Using Tabu Search for Design Automation of VLSI Systems. - John Marty Emmert; Sandeep Lodha; Dinesh Bhatia (J. Heuristics, 2003)

Estimating Pre-Placement FPGA Interconnection Requirements. - PariVallal Kannan; Dinesh Bhatia (VLSI Design, 2004)

On metrics for comparing interconnect estimation methods for FPGAs. - PariVallal Kannan; Shankar Balachandran; Dinesh Bhatia (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Exploiting temporal idleness to reduce leakage power in programmable architectures. - Rajarshee P. Bharadwaj; Rajan Konar; Poras T. Balsara; Dinesh Bhatia (ASP-DAC, 2005)

Timing Aware Interconnect Prediction Models for FPGAs. - Shankar Balachandran; Dinesh Bhatia (FPL, 2005)

FPGA Architecture for Standby Power Management. - Rajarshee P. Bharadwaj; Rajan Konar; Dinesh Bhatia; Poras T. Balsara (FPT, 2005)

Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. - Mukesh Chugh; Dinesh Bhatia; Poras T. Balsara (IPDPS, 2005)

Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. - R. Manimegalai; E. Siva Soumya; Vaishnavi Muralidharan; Balaraman Ravindran; V. Kamakoti 001; Dinesh Bhatia (VLSI Design, 2005)

FPGA based EBCOT architecture for JPEG 2000. - Manjunath Gangadhar; Dinesh Bhatia (Microprocess. Microsystems, 2005)

A priori wirelength and interconnect estimation based on circuit characteristic. - Shankar Balachandran; Dinesh Bhatia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Generic Network Interfaces for Plug and Play NoC Based Architecture. - Sanjay Pratap Singh; Shilpa Bhoj; Dheera Balasubramanian; Tanvi Nagda; Dinesh Bhatia; Poras T. Balsara (ARC, 2006)

A leakage aware design methodology for power-gated programmable architectures. - Narayan Subramanian; Rajarshee P. Bharadwaj; Dinesh Bhatia (FPT, 2006)

Exploring Logic Block Granularity in Leakage Tolerant FPGA. - Rajan Konar; Rajarshee P. Bharadwaj; Dinesh Bhatia; Poras T. Balsara (VLSI Design, 2006)

Interconnect estimation for FPGAs. - PariVallal Kannan; Dinesh Bhatia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Pre-route Interconnect Capacitance and Power Estimation in FPGAs. - Shilpa Bhoj; Dinesh Bhatia (FPL, 2007)

Thermal Modeling and Temperature Driven Placement for FPGAs. - Shilpa Bhoj; Dinesh Bhatia (ISCAS, 2007)

A dynamic temperature control simulation system for FPGAs. - Shilpa Bhoj; Dinesh Bhatia (FPL, 2008)

Early stage FPGA interconnect leakage power estimation. - Shilpa Bhoj; Dinesh Bhatia (ICCD, 2008)

Power efficient multi-band contextual activity monitoring for assistive environments. - A. L. Praveen Aroul; Achutan Manohar; Dinesh Bhatia; Leonardo Estevez (PETRA, 2008)

Study of performance and propagation characteristics of wire and planar structures around human body. - A. L. Praveen Aroul; Dinesh Bhatia (EMBC, 2011)

Antenna designs for wearable body sensor communication. - Dinesh Bhatia; A. L. Praveen Aroul (PETRA, 2013)

Growth of neural engineering and neuro-mechanics in India: physically challenged looking towards a bright future. - Dinesh Bhatia (Int. J. Medical Eng. Informatics, 2013)

Impact of communication technology on human brain activity: mobile phone vs. landline phone. - Aruna Tyagi; Manoj Duhan; Dinesh Bhatia (Int. J. Medical Eng. Informatics, 2013)

Quantitative measurement of carbon monoxide level in closed environment. - Abhishek Agarwal; Dinesh Bhatia (Int. J. Medical Eng. Informatics, 2014)

A smart door access system using finger print biometric system. - Anu; Dinesh Bhatia (Int. J. Medical Eng. Informatics, 2014)

Design of smart functional electric stimulator for physically challenged person. - Devender Singh; Manvinder Kaur; Dinesh Bhatia (Int. J. Medical Eng. Informatics, 2014)

Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). - Pingakshya Goswami; Dinesh Bhatia (FPGA, 2016)

Comparison of muscle activation patterns among healthy males and females during different lower limb movements. - Shilpi Mathur; Manvinder Kaur; Dinesh Bhatia; Suresh Verma (Int. J. Medical Eng. Informatics, 2016)

Portable impedance measurement device for sweat based glucose detection. - Athul Asokan Thulasi; Dinesh Bhatia; Poras T. Balsara; Shalini Prasad (BSN, 2017)

MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (FPGA, 2020)

Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs. - Pingakshya Goswami; Dinesh Bhatia (CoRR, 2020)

Empirical greedy machine-based automatic liver segmentation in CT images. - Gajendra Kumar Mourya; Dinesh Bhatia; Akash Handique (IET Image Process., 2020)

Resource and Performance Estimation for CNN Models using Machine Learning. - Masoud Shahshahani; Dinesh Bhatia (ISVLSI, 2021)

An Automated Tool for Implementing Deep Neural Networks on FPGA. - Masoud Shahshahani; Mohammad Sabri Abrebekoh; Bahareh Khabbazan; Dinesh Bhatia (VLSID, 2021)

Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. - Pingakshya Goswami; Dinesh Bhatia (ISQED, 2022)

MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (LASCAS, 2022)

PPA Based CNN Architecture Explorer. - Masoud Shahshahani; Dinesh Bhatia (LASCAS, 2022)

Robust Estimation of FPGA Resources and Performance from CNN Models. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (VLSID, 2022)

Enhancing Student Engagement in Engineering and Education Through Virtual Reality: A Survey-Based Analysis. - Dinesh Bhatia; Henrik Hesse (TENCON, 2023)

Application of Machine Learning in FPGA EDA Tool Development. - Pingakshya Goswami; Dinesh Bhatia (IEEE Access, 2023)

Feed Forward Neural Network BCI-based trajectory-controlled Lower-limb exoskeleton: a Biomechatronics Approach. - Ganesh Roy; Dinesh Bhatia; Subhasis Bhaumik (Int. J. Robotics Autom., 2023)

Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. - Pingakshya Goswami; Benjamin Carrión Schäfer; Dinesh Bhatia (Integr., 2023)

Advancing Towards a Wearable Ultrasound Sensor for Real-Time Bladder Volume Monitoring to Reduce Catheterization in Surgical Settings. - Rouzbeh Molaei Imenabadi; Mojtaba Hasanpour Avanji; Dinesh Bhatia; Katherine Brown (EMBC, 2024)