An overview of library characterization in semi-custom design. - Binay Ackalloor; Dinesh Gaitonde (CICC, 1998)

Instruction level power model of microcontrollers. - Chaitali Chakrabarti; Dinesh Gaitonde (ISCAS (1), 1999)

High capacity and high performance 20nm FPGAs. - Steve Young; Dinesh Gaitonde (Hot Chips Symposium, 2014)

Enhancements in UltraScale CLB Architecture. - Shant Chandrakar; Dinesh Gaitonde; Trevor Bauer (FPGA, 2015)

Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. - Henri Fraisse; Abhishek Joshi; Dinesh Gaitonde; Alireza Kaviani (FPGA, 2016)

A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. - Henri Fraisse; Dinesh Gaitonde (FPL, 2018)

Placement Strategies for 2.5D FPGA Fabric Architectures. - Chirag Ravishankar; Dinesh Gaitonde; Trevor Bauer (FPL, 2018)

SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. - Chirag Ravishankar; Henri Fraisse; Dinesh Gaitonde (FPT, 2018)

Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture. - Brian Gaide; Dinesh Gaitonde; Chirag Ravishankar; Trevor Bauer (FPGA, 2019)

Network-on-Chip Programmable Platform in VersalTM ACAP Architecture. - Ian Swarbrick; Dinesh Gaitonde; Sagheer Ahmad; Brian Gaide; Ygal Arbel (FPGA, 2019)

Versal Network-on-Chip (NoC). - Ian Swarbrick; Dinesh Gaitonde; Sagheer Ahmad; Bala Jayadev; Jeff Cuppett; Abbas Morshed; Brian Gaide; Ygal Arbel (Hot Interconnects, 2019)

A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. - Abhishek Kumar Jain; Hossein Omidian; Henri Fraisse; Mansimran Benipal; Lisa Liu; Dinesh Gaitonde (FPL, 2020)

Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. - Abhishek Kumar Jain; Sharan Kumar; Aashish Tripathi; Dinesh Gaitonde (HPEC, 2021)

100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. - Hossein Omidian; Eddie Hung; Dinesh Gaitonde (ARC, 2022)

Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. - Abhishek Kumar Jain; Chirag Ravishankar; Hossein Omidian; Sharan Kumar; Maithilee Kulkarni; Aashish Tripathi; Dinesh Gaitonde (FCCM, 2023)

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. - Shashwat Shrivastava; Stefan Nikolic 001; Chirag Ravishankar; Dinesh Gaitonde; Mirjana Stojilovic (FPGA, 2023)

AMD Next-Generation FPGA Built from Chiplets. - Dinesh Gaitonde (HCS, 2023)

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. - Shashwat Shrivastava; Stefan Nikolic 001; Chirag Ravishankar; Dinesh Gaitonde; Mirjana Stojilovic (ICCAD, 2023)

Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs. - Arun Iyer; Nishant Pawar; Dinesh Gaitonde; Nanditha Rao (ICFPT, 2024)

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. - Shashwat Shrivastava; Stefan Nikolic 001; Sun Tanaka; Chirag Ravishankar; Dinesh Gaitonde; Mirjana Stojilovic (FCCM, 2025)